SC2542 datasheet(20/27 Pages) SEMTECH

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SC2542

POWER MANAGEMENT

(

)

RMS

DS ON

where Rds(on) is the channel resistance of bottom MOS-

FET. If the input voltage to output voltage ratio is high

(e.g. Vin = 12V, Vo = 1.5V), the duty ratio D will be small.

Since the bottom switch conducts with duty ratio (1-D),

the corresponding conduction losses can be quite high.

Due to non-overlapping conduction between the top and

the bottom MOSFET, the internal body diode or the ex-

ternal Schottky diode across the drain and source termi-

nals always conducts prior to the turn on of the bottom

MOSFET. The bottom MOSFET switches on with only a

diode voltage between its drain and source terminals.

The switching loss is negligible due to near zero-voltage

switching.

The gate losses are estimated as:

The total bottom switch losses are then:

Once the power losses for the top and bottom MOSFET

are known, thermal and package design at component

and system level should be done to verify that the maxi-

mum die junction temperature (Tj,max, usually 125°C) is

not exceeded under the worst-case condition. The equiva-

lent thermal impedance from junction to ambient (

JA)

should satisfy:

JMAX

A MAX

LOSS

−

≤

JA depends on the die to substrate bonding, packaging

material, the thermal contact surface, thermal compound

property, the available effective heat sink area, and the

air flow condition (natural or forced convection). Actual

temperature measurement of the prototype should be

carried out to verify the thermal design.

PC Board Layout Issues

Circuit board layout is very important for the proper op-

eration of high frequency switching power converters. A

power ground plane is required to reduce ground bounces.

The followings are suggested for proper layout.

Power Stage

1) Separate the power ground from the signal ground. In

SC2542 design, use an isolated local ground plane for

the controller and tie it to power grand.

2) Minimize the size of the high pulse current loop. Keep

the top MOSFET, the bottom MOSFET and the input ca-

pacitors within a small area with short and wide traces.

In addition to the aluminum energy storage capacitors,

add multi-layer ceramic (MLC) capacitors from the input

to the power ground to improve high frequency bypass.

3) Reduce high frequency voltage ringing. Widen and

shorten the drain and source traces of the MOSFETs to

reduce stray inductances. Add a small RC snubber if nec-

essary to reduce the high frequency ringing at the phase

node. Sometimes slowing down the gate drive signal also

helps in reducing the high frequency ringing at the phase

node if the EMI is a concern for the system.

4) Shorten the gate drive trace. Integrity of the gate

drive (voltage level, leading and falling edges) is impor-

tant for circuit operation and efficiency. Short and wide

gate drive traces reduce trace inductances. Bond wire

inductance is about 2~3nH. If the length of the PCB

trace from the gate driver to the MOSFET gate is 1 inch,

the trace inductance will be about 25nH. If the gate drive

current is 2A with 10ns rise and falling times, the voltage

drops across the bond wire and the PCB trace will be

0.6V and 5V respectively. This may slow down the switch-

ing transient of the MOSFET. These inductances may also

ring with the gate capacitance.

5) Put the decoupling capacitor for the gate drive power

supplies (BST and PVCC) close to the IC and power ground.

Control Section

6) The frequency-setting resistor Rosc should be placed

close to Pin 23. Trace length from this resistor to the

analog ground should be minimized.

7) Place the bias decoupling capacitor right across the

VCC and analog ground AGND.

Applications Information (Cont.)

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