ADS7846

4

SBAS125H

www.ti.com

PIN CONFIGURATION

Top View

SSOP, TSSOP

Top View

VFBGA

1

2

3

4

5

6

7

8

+V

CC

X+

Y+

X–

Y–

GND

V

BAT

AUX

DCLK

CS

DIN

BUSY

DOUT

PENIRQ

+V

CC

V

REF

16

15

14

13

12

11

10

9

ADS7846

NC

NC

A

2

1

3

4

5

6

7

DCLK

+V

CC

+V

CC

X+

Y+

PENIRQ

+V

CC

V

REF

AUX

CS

DIN

BUSY DOUT

X–

Y–

GND

GND

V

BAT

NC

NC

NC

NC

NC

B

C

D

E

F

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

G

BUSY

DIN

CS

DCLK

AUX

V

BAT

GND

Y–

1

2

3

4

12

11

10

9

ADS7846

Top View

QFN

SSOP AND

TSSOP PIN #

VFBGA PIN #

QFN PIN #

NAME

DESCRIPTION

1

B1 and C1

5

+VCC

Power Supply

2

D1

6

X+

X+ Position Input

3

E1

7

Y+

Y+ Position Input

4G2

8

X–

X– Position Input

5G3

9

Y–

Y– Position Input

6

G4 and G5

10

GND

Ground

7G6

11

VBAT

Battery Monitor Input

8

E7

12

AUX

Auxiliary Input to ADC

9D7

13

VREF

Voltage Reference Input/Output

10

C7

14

+VCC

Digital I/O Power Supply

11

B7

15

PENIRQ

Pen Interrupt. Open anode output (requires 10k

Ω to 100kΩ pull-up resistor externally).

12

A6

16

DOUT

Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high

impedance when CS is high.

13

A5

1

BUSY

Busy Output. This output is high impedance when CS is high.

14

A4

2

DIN

Serial Data Input. If CS is low, data is latched on rising edge of DCLK.

15

A3

3

CS

Chip Select Input. Controls conversion timing and enables the serial input/output register.

CS high = power-down mode (ADC only).

16

A2

4

DCLK

External Clock Input. This clock runs the SAR conversion process and synchronizes serial data

I/O.

PIN DESCRIPTION