ADS7846 datasheet(13/29 Pages) SYC

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ADS7846

SBAS125H

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sample-and-hold goes into the hold mode and the touch

panel drivers turn off (in single-ended mode). The next 12

clock cycles accomplish the actual analog-to-digital conver-

sion. If the conversion is ratiometric (SER/DFR = 0), the

drivers are on during the conversion and a 13th clock cycle

is needed for the last bit of the conversion result. Three more

clock cycles are needed to complete the last byte (DOUT will

be low), which are ignored by the converter.

Control Byte

The control byte (on DIN), as shown in Table III, provides the

start conversion, addressing, ADC resolution, configuration,

and power-down of the ADS7846. Figure 9 and Tables III

and IV give detailed information regarding the order and

description of these control bits within the control byte.

SER/DFR—The SER/DFR bit controls the reference mode,

either single-ended (high) or differential (low). The differential

mode is also referred to as the ratiometric conversion mode

and is preferred for X-Position, Y-Position, and Pressure-

Touch measurements for optimum performance. The refer-

ence is derived from the voltage at the switch drivers, which

is almost the same as the voltage to the touch screen. In this

case a reference voltage is not needed, as the reference

voltage to the ADC is the voltage across the touch screen. In

the single-ended mode, the converter reference voltage is

always the difference between the VREF and GND pins (see

Tables I and II, and Figures 2 through 5 for further informa-

tion).

If X-Position, Y-Position, and Pressure-Touch are measured

in the single-ended mode, an external reference voltage is

needed. The ADS7846 should also be powered from the

external reference. Caution must be observed when using

the single-ended mode such that the input voltage to the

ADC does not exceed the internal reference voltage, espe-

cially if the supply voltage is greater than 2.7V.

NOTE: The differential mode can only be used for X-Position,

Y-Position, and Pressure-Touch measurements. All other

measurements require the single-ended mode.

PD0 and PD1—Table V describes the power-down and the

internal reference voltage configurations. The internal refer-

ence voltage can be turned on or off independently of the

ADC. This can allow extra time for the internal reference

voltage to settle to the final value prior to making a conver-

sion. Make sure to also allow this extra wake-up time if the

internal reference is powered down. The ADC requires no

wake-up time and can be instantaneously used. Also note

that the status of the internal reference power-down is

latched into the part (internally) with BUSY going high.

Therefore, in order to turn the reference off, an additional

write to the ADS7846 is required after the channel is con-

verted.

Bit 7

Bit 0

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

MODE SER/DFR

PD1

PD0

TABLE III. Order of the Control Bits in the Control Byte.

BIT

NAME

DESCRIPTION

Start Bit. Control byte starts with first high bit on DIN.

A new control byte can start every 15th clock cycle

in 12-bit conversion mode or every 11th clock cycle

in 8-bit conversion mode (see Figure 12).

6-4

A2-A0

Channel Select Bits. Along with the SER/DFR bit,

these bits control the setting of the multiplexer input,

touch driver switches, and reference inputs (see

Tables I and II).

MODE

12-Bit/8-Bit Conversion Select Bit. This bit controls

the number of bits for the next conversion: 12-bits

(low) or 8-bits (high).

SER/DFR

Single-Ended/Differential Reference Select Bit. Along

with bits A2-A0, this bit controls the setting of the

multiplexer input, touch driver switches, and reference

inputs (see Tables I and I).

1-0

PD1-PD0

Power-Down Mode Select Bits. See Table V for

details.

TABLE IV. Descriptions of the Control Bits within the Control

Byte.

Initiate START—The first bit, the S bit, must always be high

and initiates the start of the control byte. The ADS7846

ignores inputs on the DIN pin until the start bit is detected.

Addressing—The next three bits (A2, A1, and A0) select the

active input channel(s) of the input multiplexer (see Tables I,

II, and Figure 2), touch screen drivers, and the reference

inputs.

MODE—The mode bit sets the resolution of the ADC. With

this bit low, the next conversion has 12 bits of resolution; with

this bit high, the next conversion has 8 bits of resolution.

PD1

PD0

PENIRQ

DESCRIPTION

Enabled

Power-Down Between Conversions. When each

conversion is finished, the converter enters a

low-power mode. At the start of the next conver-

sion, the device instantly powers up to full power.

There is no need for additional delays to assure

full operation and the very first conversion is

valid. The Y– switch is on when in power-down.

Disabled

Reference is off and ADC is on.

Enabled

Reference is on and ADC is off.

Disabled

Device is always powered. Reference is on and

ADC is on.

TABLE V. Power-Down and Internal Reference Selection.

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