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AD8178 Datasheet(PDF) 17 Page - Analog Devices |
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AD8178 Datasheet(HTML) 17 Page - Analog Devices |
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17 / 40 page  AD8178 Rev. 0 | Page 17 of 40 TRUTH TABLE AND LOGIC DIAGRAM Table 15. Operation Truth Table WE UPDATE CLK SERIN SEROUT RST SER/PAR CS CMENC Operation/Comment X1 X X X X 0 X X X Asynchronous reset. All outputs are disabled. Contents of the 45-bit shift register are unchanged. 1 1 SERINi SERINi-45 1 0 0 X Serial mode. The data on the SERIN line is loaded into the 45-bit shift register. The first bit clocked into the shift register appears at SEROUT 45 clock cycles later. Data is not applied to the switch array. 0 1 1 X X 1 1 0 X Parallel mode. The data on parallel lines D0 through D4 is loaded into the shift register location addressed by A0 through A2. Data is not applied to the switch array. 1 0 1 X X 1 X 0 X Switch array update. Data in the 45-bit shift register is trans- ferred to the parallel latches and applied to the switch array. 1 X X X X 1 1 0 X No change in logic. 1 X = don’t care. |
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