RT9643

4

DS9643-03 August 2007

www.richtek.com

To eliminate the “bump” add delay to the 5V_MAIN pin as shown below. The 5V_MAIN pin on the RT9643 does not

supply power to the IC, it is only used to monitor the voltage level of the 5V_MAIN supply.

Figure 2. S3 to S0 Transition (5V DUAL)

Figure 3. Adding Delay to 5V_MAIN

Another method to eliminate the potential for this “bump” is to use the PWR_OK to drive the 5V_MAIN pin. Some

systems cannot tolerate the long delay for PWR_OK (>100ms) to assert, hence the solution in figure C may be

preferable.

S5 to S3 :

MAIN is below its UVLO threshold. At that time, 5V Dual is charged. The limited gate drive controls the inrush current

through Q4 as it charges C1 (Capacitance on 5V Dual). Depending on the CGD of Q4, the current available from 5VSB,

and the size of C1, C13 may be omitted.

GD(Q4)

7

Q4(INRUSH)

C

C13

10

x

5

x

C1

I

+

=

−

S3 to S0 :

The system signals this transition by raising the S3#I signal. S0 mode is not entered until 5V_MAIN o.k..

Then the following occurs :

5VSB_DRV pulls high to turn off the P-Channel switch.

The 3.3V LDO turns off.

In most systems, the ATX power supply is enabled when S3#I goes to high. At that point, 5V_MAIN and 3.3 MAIN will

start to rise. The RT9643 waits until 5V_MAIN is above 4.5V to turn on Q3 and Q5. This can cause about a 10% “bump”

in both 5V DUAL and 3.3V DUAL when Q3 and Q5 turn on, since at that point, 5V_MAIN and 3.3 MAIN are at 90% of their

regulation value.

4.4V

5V Dual

5V_MAIN

VCC_EN

S3#I

5V_MAIN

from ATX

5V_MAIN

to RT9643