RT9643 datasheet(7/17 Pages) RICHTEK

7 / 17 page

RT9643

DS9643-03 August 2007

www.richtek.com

PHASE (Pin10)

Phase node of VDDQ PWM. The pin is applied to sense

phase node of VDDQ PWM for gates switch control.

ISNS (Pin11)

Current Sense input. Monitors the voltage drop across

the low-side MOSFET or external sense resistor for over

current control.

LGATE (Pin12)

Low-Side Drive. The low-side MOSFET driver output.

Connect to gate of low-side MOSFET.

PGOOD (Pin13)

Power Good Indication Signal. An open-drain output signal

that will pull LOW if FB is outside of a

±10% range of the

0.9V reference and the LDO outputs are > 80% or < 110%

of its reference. PGOOD goes low when S3 is high. The

power good signal from the PWM regulator enables the

VTT regulator and the LDO controller.

VCC (Pin14)

IC VCC. 5VSB is generally applied for bias power for IC

logics and gate driver control. The IC stays at standby

until this pin is higher than 4.35V.

3VSB_OUT (Pin15)

3.3VSB LDO Output. Internal linear regulator and is

capable to drive up to 1.25Amp peak current. The power

is Turned off in S0 state, and on in S5 or S3 stage.

VCC_EN (Pin16)

VCC enable signal for dual power. The pin is applied to

control VCC power on for 3.3VDL and 5VDL, the signal is

an open drain output which pulls the gate of an two N-

Channel blocking MOSFETs low in S5 and S3. This pin

goes high (open) in S0.

S3#I (Pin17)

S3 Input. When LOW, the VTT and 1.2V LDO regulators

are turned off and 3.3VSB regulator is turned on the.

PGOOD is set to low when S3#I is LOW.

EN (Pin18)

Chip ENABLE. Typically tied to S5#. When this pin is

low, the IC is operated in standby mode, all regulators are

off and VCC_EN is low.

GND [Pin19, Exposed Pad (25)]

IC GROUND. The ground power for whole chip. The

exposed pad must be soldered to a large PCB and

connected to GND for maximum power dissipation.

ILIM (Pin20)

Current Limit setting pin. A external resistor is attached

to set the current limit value.

SS (Pin21)

Soft Start. A external capacitor is attached to control the

slew rate of the converter during initialization as well as

sets the initial slew rate of the LDO controllers when

transitioning from S3 to S0. This pin is charged/discharged

with a internal 5uA current source during initialization,

and charged with 50uA during PWM soft-start.

COMP (Pin22)

Compensation pin of VDDQ PWM. Output of the PWM

error amplifier. Connect compensation network between

this pin and FB.

FB (Pin23)

VDDQ PWM Feedback. The output feedback of VDDQ

PWM. The pin is applied for voltage regulation, PGOOD,

under-voltage, and over-voltage protection and monitoring.

REF_IN (Pin24)

VTT voltage setting. The VTT regulator tracks the voltage

set the pin, typically, it should be 1/2VDDQ

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