RT9643 datasheet(11/17 Pages) RICHTEK

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RT9643

DS9643-03 August 2007

www.richtek.com

source. The output voltage starts to go up when VCSS is

larger than 0.4V. To prevent large duty cycles and high

currents during the beginning of the PWM soft-start, Once

CSS has charged to 1.3V, the output voltage will be in

regulation.

The time it takes SS to reach 1.3V is :

where T1.3 is in ms if CSS is in nF.

The PWM regulator’ s latched faults are enabled until CSS

charges up to 1.5V. When CSS reaches 2.5V, the VTT

and 1.2V LDO will begin their soft-start ramps. After the

VTT and 1.2V LDO regulators are in regulation, PGOOD

is then allowed to go HIGH (open). UVLO on VCC will

discharge SS and reset the IC.

Current Sensing Section

Application Information

PWM Regulator

The RT9643 combines a single-phase synchronous buck

PWM controller designed to drive two N-Channel

MOSFETs. It provides a highly accurate, programmable

output voltage precisely regulated to low voltage

requirement with an internal 0.9V reference.

Setting the output voltage

The output voltage of the PWM regulator can be set in the

range of 0.9V to 90% of its power input by an external

resistor divider.

The internal reference is 0.9V. The output is divided down

by an external voltage divider to the FB pin (for example,

R1 and R2 in Typical Application Circuit). There is also a

μA precision (±5%) current sourced out of FB to ensure

that if the pin is open, VDDQ will remain low. The output

voltage therefore is :

To minimize noise pickup on this node, keep the resistor

to GND (R2) below 2k. We selected R2 at 1.82k and solved

for R1.

The synchronous buck converter is optimized for 5V

operation.

Oscillator

The internal oscillator frequency is 300kHz. The internal

PWM ramp is reset on the rising clock edge.

PWM Soft Start

When the PWM regulator is enabled the circuit will wait

until the VDDQ_IN pin is below 100mV to ensure that the

soft-start cycle does not begin with a large residual voltage

on the PWM regulator output.

When the PWM regulator is disabled, 50

Ω is turned on

from VDDQ_IN to PGND to discharge the output.

The voltage at the positive input of the error amplifier is

limited to VCSS which is charged with a 50

μA current

0.9V

OUT

−

1.82k

1.816k

A x

0.9

0.9)

OUT

≈

−

1.3

The following discussion refers to Figure 4.

The current through RSENSE resistor (ISNS) is sensed

shortly after low side MOSFET is turned on.

Setting the Current Limit

An ISNS is compared to the current established when a

0.9 V internal reference drives the ILIM pin. RILIM, the

RDS(ON) of Q2, and RSENSE determine the current limit :

Figure 4. Current Sense & Limit

Current Sense

ILIM x 10

0.9V

ILIM Mirror

2.5V

ILIM det.

RSENSE

ISNS

PGND

ILIM RILIM

DS(ON)

SENSE

LIMIT

ILIM

0.9

Where ILIMIT is the peak inductor current. Since the

tolerance on the current limit is largely dependent on the

ratio of the external resistors it is fairly accurate if the

voltage drop on the Switching Node side of RSENSE is an

accurate representation of the load current.

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