RT9643 datasheet(12/17 Pages) RICHTEK

12 / 17 page

RT9643

DS9643-03 August 2007

www.richtek.com

REF

OUT

COMP

Figure 5. Compensation Network

PGOOD Signal

PGOOD monitors the status of the PWM output as well

as the VTT and 1.2V LDO regulators. PGOOD remains

low unless all of the conditions below are met :

1. S3#I is HIGH

2. SS is above 4V

3. Fault latch is cleared

4. FB is between 90% and 110% of VREF

5. VTT and 1.2V LDO regulators are in regulation

Protection

The converter output is monitored and protected against

extreme overload, short circuit, over-voltage and under-

voltage conditions.

An internal “Fault Latch” is set for any fault intended to

shut down the IC. When the “Fault Latch” is set, the IC

will discharge VDDQ_IN by driving LGATE high until

VDDQ_IN < 0.5V. LGATE will then go low until VDDQ_IN >

0.8V. This behavior will discharge the output without

causing undershoot (negative output voltage).

When using the MOSFET as the sensing element, the

variation of RDS(ON) causes proportional variation in the

ISNS. This value not only varies from device to device,

but also has a typical junction temperature coefficient of

about 0.4%/

°C (consult the MOSFET datasheet for actual

values), so the actual current limit set point will decrease

proportional to increasing MOSFET die temperature. A

factor of 1.6 in the current limit set point should compensate

for all MOSFET RDS(ON) variations, assuming the

MOSFET’ s heat sinking will keep its operating die

temperature below 125

°C.

Current limit (ILIMIT) should be set sufficiently high as to

allow inductor current to rise in response to an output

load transient. Typically, a factor of 1.3 is sufficient. In

addition, since ILIMIT is a peak current cut-off value, we

will need to multiply ILOAD(MAX) by the inductor ripple current

(20% is chosen).

ILIMIT > ILOAD(MAX) x 1.6 x 1.3 x 1.2

Gate Driver Section

The adaptive gate control logic translates the internal PWM

control signal into the MOSFET gate drive signals providing

necessary amplification, level shifting and shoot-through

protection. Also, it has functions that help optimize the IC

performance over a wide range of operating conditions.

Since MOSFET switching time can vary dramatically from

type to type and with the input voltage, the gate control

logic provides adaptive dead time by monitoring the gate

to source voltages of both upper and lower MOSFETs.

The lower MOSFET drive is not turned on until the PHASE

has decreased to less than approximately one VT

(~0.6volt). Similarly, the upper MOSFET is not turned on

until the gate-to-source voltage of the lower MOSFET has

decreased to less than approximately one VT (~0.6 volt).

This allows a wide variety of upper and lower MOSFETs

to be used without a concern for simultaneous conduction,

or shoot-through.

There must be a low-resistance, low-inductance path

between the driver pin and the MOSFET gate for the

adaptive dead-time circuit to work properly. Any delay along

that path will subtract from the delay generated by the

adaptive dead-time circuit and shoot-through may occur.

Frequency Loop Compensation

The loop is compensated using a feedback network around

the error amplifier, which is a voltage output OP Amp.

Figure 5 shows a complete type3 compensation network.

A type2 compensation configuration eliminates R3 and

C3 and is shown in typical application circuit. Type2

compensation can be used for most applications. For

critical applications that require wide loop-bandwidth, and

use very low ESR output capacitors, type3 compensation

may be required.

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