PCAL9722 datasheet(3/63 Pages) NXP

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NXP Semiconductors

PCAL9722

Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and

reset

2 Features and benefits

• SPI bus to parallel port expander

• 5 MHz SPI bus

• Operating power supply voltage range of 1.1 V to 5.5 V on the SPI bus side

• Allows bidirectional voltage-level translation and GPIO expansion between 1.1 V to 5.5 V on SPI and 1.8 V,

2.5 V, 3.3 V, 5.5 V on Port P

• Low standby current consumption: 2.0 μA typical at 3.3 V VDD

• Schmitt trigger action allows slow input transition and better switching noise immunity at the SPI inputs

(SCLK, SDIN, CS)

– Vhys = 0.11 V (typical) at 1.1 V

– Vhys = 0.18 V (typical) at 1.8 V

– Vhys = 0.33 V (typical) at 3.3 V

– Vhys = 0.55 V (typical) at 5.5 V

• 5.5 V tolerant I/O ports and SPI bus pins

• Active LOW reset input (RESET)

• Open-drain active LOW interrupt output (INT)

• Internal power-on reset

• Noise filter on SPI inputs

• Latched outputs with 25 mA drive maximum capability for directly driving LEDs

• Latch-up performance exceeds 100 mA per JESD 78, Class II

• ESD protection exceeds JESD 22

– 2000 V Human-Body Model (A114-A)

– 1000 V Charged-Device Model (C101)

• Package offered: HVQFN32

2.1 Agile I/O features

• Output port configuration: bank selectable or pin selectable push-pull or open-drain output stages

• Interrupt status: read-only register identifies the source of an interrupt

• Bit-wise I/O programming features:

– Output drive strength: four programmable drive strengths to reduce rise and fall times in low-capacitance

applications

– Input latch: Input Port register values changes are kept until the Input Port register is read

– Pull-up/pull-down enable: floating input or pull-up/pull-down resistor enable

– Pull-up/pull-down selection: 100 kΩ pull-up/pull-down resistor selection

– Interrupt mask: mask prevents the generation of the interrupt when input changes state to prevent spurious

interrupts

2.2 Additional Agile I/O Plus features

• Interrupt edge specification on a bit-by-bit basis

• Interrupt individual clear without disturbing other events

• Read all interrupt events without clear

• Switch debounce hardware

PCAL9722

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 1 May 2023

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