PCAL9722 datasheet(9/63 Pages) NXP

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NXP Semiconductors

PCAL9722

Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and

reset

registers sequentially without modifying the pointer register. The contents of these bits will roll over to ‘000 0000’

after the last register (address = 76h) is accessed. Unimplemented register addresses (reserved registers) are

skipped. If more than 52 bytes are written, the address will loop back to the register which is indicated by the

seven low-order bits in the pointer register, and previously-written data will be overwritten. The de-assertion of

chip select (CS) condition will keep the pointer register value in the last read or write location.

When the Auto-Increment bit is cleared (AI = 0), the 2 least significant bits are automatically incremented after

a read or write for 3-register group which allows the user to program each of the 3-register group sequentially.

If more than 3 bytes of data are read or written when AI is 0, previous data in the selected registers will be

overwritten. For example: if input port 1 is read first, the next 2nd byte will be input port 2, and next 3nd byte

will be input port 0, there is no limit on the number of data bytes for this read operation. There are two special

6-register groups: output drive strength (40h~45h) and interrupt edge (60h~65h) registers will allow user

to program each of the 6-register group sequentially. Only Output port configuration register location (5Ch)

remains in the same location after a successive read or write.

aaa-015941

default value at power-up

or HW reset

AI B6 B5 B4 B3 B2 B1 B0

AI = Auto-Increment

Figure 4. Pointer register bits

Pointer register bits

B6 B5 B4 B3 B2 B1 B0

Command

byte

(hexadecimal)

Protocol

Power-up

default

00h

Input port 0

read byte

xxxx xxxx[1]

01h

Input port 1

read byte

xxxx xxxx[1]

02h

Input port 2

read byte

xxxx xxxx[1]

03h

reserved[2]

reserved

04h

Output port 0

read/write byte 1111 1111

05h

Output port 1

read/write byte 1111 1111

06h

Output port 2

read/write byte 1111 1111

07h

reserved[2]

reserved

08h

Polarity Inversion port 0

read/write byte 0000 0000

09h

Polarity Inversion port 1

read/write byte 0000 0000

0Ah

Polarity Inversion port 2

read/write byte 0000 0000

0Bh

reserved[2]

reserved

0Ch

Configuration port 0

read/write byte 1111 1111

0Dh

Configuration port 1

read/write byte 1111 1111

0Eh

Configuration port 2

read/write byte 1111 1111

0Fh to 3Fh

reserved[2]

reserved

40h

Output drive strength register port 0A read/write byte 1111 1111

41h

Output drive strength register port 0B read/write byte 1111 1111

Table 6. Command byte

PCAL9722

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Product data sheet

Rev. 1.1 — 1 May 2023

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