PCAL9722 datasheet(49/63 Pages) NXP

49 / 63 page

NXP Semiconductors

PCAL9722

Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and

reset

aaa-015953

DUT

CL = 100 pF

500

2 × VDD(P)

500

a. P port load configuration

1 0 0 0 0 0 0

slave address

data from port 0

data from port 1

unstable

data

SDIN

SDOUT

DATA 01

DATA 11

0 0 0 0 0 0 0

R/W

SCLK

P0n

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

27 28 29 30 31 32

P1n

DATA 11

aaa-015954

View A - A

SCLK

24th

tv(Q)

0.3 × VDD(SPI)

0.7 × VDD(SPI)

DATA 01

b. Write mode (R/W = 0)

SCLK

24th

0.3 × VDD(SPI)

0.5 × VDD(P)

0.7 × VDD(SPI)

th(D)

tsu(D)

aaa-015955

CL includes probe and jig capacitance.

tv(Q) is measured from 0.7 × VDD(SPI) on SCLK to 50 % I/O (Pn) output.

All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr/tf ≤ 30 ns.

The outputs are measured one at a time, with one transition per measurement.

All parameters and waveforms are not applicable to all devices.

c. Read mode (R/W = 1)

Figure 30. P port load circuit and voltage waveforms

PCAL9722

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 1 May 2023

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