PCAL9722 datasheet(32/63 Pages) NXP

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NXP Semiconductors

PCAL9722

Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and

reset

002aag961

VDD(P)

time

ramp-down

(dV/dt)f

ramp-up

(dV/dt)r

time to re-ramp

when VDD(P) drops

to VPOR(min) - 50 mV

td(rst)

VI drops below POR levels

Figure 17. VDD(P) is lowered below the POR threshold, then ramped back up to VDD(P)

Table 60 specifies the performance of the power-on reset feature for PCAL9722 for both types of power-on

reset.

Tamb = 25 °C (unless otherwise noted). Not tested; specified by design.

Symbol

Parameter

Condition

Min

Typ

Max

Unit

(dV/dt)f

fall rate of change of voltage

Figure 16

0.1

2000

(dV/dt)r

rise rate of change of voltage

Figure 16

0.1

2000

Figure 16; re-ramp time when

VDD(P) drops below 0.2 V or to VSS

μs

td(rst)

reset delay time

Figure 17; re-ramp time when

VDD(P) drops to VPOR(min) - 50 mV

μs

ΔVDD(gl)

glitch supply voltage difference

Figure 18

[1] -

1.0

tw(gl)VDD

supply voltage glitch pulse width

Figure 18

[2] -

μs

falling VDD(P)

0.7

VPOR(trip)

power-on reset trip voltage

rising VDD(P)

1.5

Table 60. Recommended supply sequencing and ramp rates

[1]

Level that VDD(P) can glitch down to with a ramp rate at 0.4 μs/V, but not cause a functional disruption when tw(gl)VDD < 1 μs.

[2]

Glitch width that will not cause a functional disruption when ΔVDD(gl) = 0.5 × VDD(P).

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch

width (tw(gl)VDD) and glitch height (ΔVDD(gl)) are dependent on each other. The bypass capacitance, source

impedance, and device impedance are factors that affect power-on reset performance. Figure 18 and Table 60

provide more information on how to measure these specifications.

002aag962

VDD(P)

time

tw(gl)VDD

VDD(gl)

Figure 18. Glitch width and glitch height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released

and all the registers and the SPI bus state machine are initialized to their default states. The value of VPOR

differs based on the VDD being lowered to or from 0 V. Figure 19 and Table 60 provide more details on this

specification.

PCAL9722

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 1 May 2023

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