PCAL9722 datasheet(1/63 Pages) NXP

Part #	PCAL9722

Description	Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and reset

PDF	63 Pages

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Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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PCAL9722

Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features,

interrupt output and reset

Rev. 1.1 — 1 May 2023

Product data sheet

1 General description

The PCAL9722 is a 22-bit general purpose I/O expander that provides remote I/O expansion for most

microcontroller families via the SPI interface. The ultra low-voltage interface allows for direct connection to a

microcontroller operating down to 1.1 V.

NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections

to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push buttons,

keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running

at one voltage level down to 1.1 V to I/O devices operating at a different voltage level 1.65 V to 5.5 V. The

PCAL9722 has built-in level shifting feature that makes these devices extremely flexible in mixed power

supply systems where communication between incompatible I/O voltages is required, allowing seamless

communications with next-generation low voltage microprocessors and microcontrollers on the interface side

(SPI) and peripherals at a higher voltage on the port side.

There are two supply voltages for PCAL9722: VDD(SPI) and VDD(P). VDD(SPI) provides the supply voltage for

the interface at the master side (for example, a microcontroller) and the VDD(P) provides the supply for core

circuits and Port P. The bidirectional voltage level translation in the PCAL9722 is provided through VDD(SPI).

VDD(SPI) should be connected to the VDD of the external SPI lines. This indicates the VDD level of the SPI to the

PCAL9722, while the voltage level on Port P of the PCAL9722 is determined by the VDD(P).

The PCAL9722 works up to 5 MHz of SCLK speed and implements Agile I/O, which are additional features

specifically designed to enhance the I/O. These additional features are: programmable output drive strength,

latchable inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register,

programmable open-drain or push-pull outputs.

Additional Agile I/O Plus features include interrupts that can be specified by level or edge, and can be cleared

individually without disturbing the other interrupt events. Also, switch debounce hardware is implemented.

At power-on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either

inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the

corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity

Inversion register, saving external logic gates. Programmable pull-up and pull-down resistors eliminate the need

for discrete components.

The system master can reset the PCAL9722 in the event of a time-out or other improper operation by asserting

a LOW in the RESET input. The power-on reset puts the registers in their default state and initializes the SPI

state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part.

The PCAL9722 open-drain interrupt (INT) output is activated when any input state differs from its corresponding

Input Port register state and is used to indicate to the system master that an input state has changed. As well,

the INT output can be specified to activate on input pin edges. There are a large number of interrupt mask

functions available to maximize flexibility.

INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the

remote I/O can inform the microcontroller if there is incoming data on its ports without communication via the

SPI bus. Thus, the PCAL9722 can remain a simple slave device. The input latch feature holds or latches the

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