NXP Semiconductors

PCAL9722

Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and

reset

Tamb = -40 °C to +125 °C; VDD(SPI) = 1.1 V to 5.5 V; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ [1] Max

Unit

VDD(P) = 3.6 V to 5.5 V; fSCLK = 0 MHZ

-

3

12

μA

VDD(P) = 2.3 V to 3.6 V; fSCLK = 0 MHZ

-

2

6.5

μA

VDD(P) = 1.65 V to 2.3 V; fSCLK =

0 MHZ

-

1.5

4.5

μA

Active mode; IDD(SPI) + IDD(P);

SCLK, SDIN, CS, P port, ADDR, RESET;

VI on SDIN, CS, ADDR, and RESET =

VDD(SPI) or VSS;

VI on P port = VDD(P); IO = 0 mA; I/O =

inputs; fSCLK = 5 MHZ;

continuous register read with 100 pF load

on SDOUT

VDD(P) = 3.6 V to 5.5 V

-

2500

4200

μA

VDD(P) = 2.3 V to 3.6 V

-

2200

3200

μA

VDD(P) = 1.65 V to 2.3 V

-

1800

2800

μA

with pull-ups enabled; IDD(SPI) + IDD(P);

P port, ADDR, RESET; VI on ADDR,

SCLK, SDIN, CS, and RESET = VDD(SPI)

or VSS;

VI on P port = VSS; IO = 0 mA;

I/O = inputs with pull-up enabled; fSCLK =

0 kHz

VDD(P) = 1.65 V to 5.5 V

-

1.65

2.4

mA

ADDR, SCLK, SDIN, CS, and RESET;

one input at VDD(SPI) - 0.6 V, other inputs

at VDD(SPI) or VSS; VDD(P) = 1.65 V to 5.5 V

-

-

30

μA

ΔIDD

additional quiescent

supply current [5]

P port; one input at VDD(P) - 0.6 V, other

inputs at VDD(P) or VSS; VDD(P) = 1.65 V to

5.5 V

-

-

80

μA

Ci

input capacitance [6]

VI = VDD(SPI) or VSS; VDD(P) = 1.65 V to

5.5 V

-

6

7

pF

VI/O = VDD(SPI) or VSS; VDD(P) = 1.65 V to

5.5 V

-

7

8

pF

Cio

input/output capacitance

[6]

VI/O = VDD(P) or VSS; VDD(P) = 1.65 V to

5.5 V

-

7.5

8.5

pF

Rpu(int)

internal pull-up resistance input/output

50

100

150

kΩ

Rpd(int)

internal pull-down

resistance

input/output

50

100

150

kΩ

Table 65. Static characteristics for PCAL9722HN/Q900...continued

[1]

For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V or 3.6 V VDD) and Tamb = 25 °C. Except for IDD, the typical values are at VDD(P)

= VDD(SPI) = 3.3 V and Tamb = 25 °C.

[2]

The total current sourced by all I/Os must be limited to 160 mA.

[3]

Each I/O must be externally limited to a maximum of 25 mA and each octal (P0_0 to P0_7 and P1_0 to P1_7) must be limited to a maximum current of

100 mA, for a device total of 200 mA.

[4]

Typical value for Tamb = 25 °C. VOL = 0.4 V and VDD(SPI) = VDD(P) = 3.3 V. Typical value for VDD(SPI) = VDD(P) < 2.5 V, VOL = 0.6 V.

[5]

Internal pull-up/pull-down resistors disabled.

[6]

Value not tested in production, but guaranteed by design and characterization.

PCAL9722

All information provided in this document is subject to legal disclaimers.

© 2023 NXP B.V. All rights reserved.

Product data sheet

Rev. 1.1 — 1 May 2023

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