TMP88CS38 datasheet(104/226 Pages) TOSHIBA

104 / 226 page

TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-104

b. Shift edge

The leading edge is used to transmit data, and the trailing edge is used to

receive data.

1. Leading edge

Data is shifted on the leading edge of the serial clock (at a falling edge of the

SCK

pin input/output).

2. Trailing edge

Data is shifted on the trailing edge of the serial clock (at a rising edge of the

SCK

pin input/output).

Figure 2.9.23 Shift Edge

(2) Transfer mode

The SIOM (Bits 5 and 4 in SBICRA) is used to select a transmit, receive, or

transmit/receive mode.

a. 8-bit transmit mode

Set a control register to a transmit mode and write transmit data to the

SBIDBR.

After the transmit data is written, set the SIOS to “1” to start data transfer. The

transmitted data is transferred from the SBIDBR to the shift register and output

to the SO pin in synchronous with the serial clock, starting from the least

significant bit (LSB). When the transmit data is transferred to the shift register,

the SBIDBR becomes empty. The INTSBI (Buffer empty) interrupt request is

generated to request new data.

When the internal clock is used, the serial clock will stop and automatic-wait

function will be initiated if new data is not loaded to the data buffer register after

the specified 8-bit data is transmitted. When transmit new data is written,

automatic-wait function is canceled.

When the external clock is used, data should be written to the SBIDBR before

new data is shifted.

The SO pin is “1” from the time transmission starts until the first data bit is

sent. When SIOF becomes “0”, the shift register is cleared. So, output of an

undefined value is not prevented at the start of the next transmission.

The transfer speed is determined by the maximum delay time between the time

when an interrupt request is generated and the time when data is written to the

SBIDBR by the interrupt service program.

SCK

SO pin

Shift register

Bit0

(a) Leading edge

SCK

SI pin

Shift register

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

76543210

*7654321

**765432

***76543

****7654

*****765

******76

*******7

Bit0

(b) Trailing edge

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

********

0*******

10******

210*****

3210****

43210***

543210**

6543210* 76543210

*: Don’t care

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