TMP88CS38 datasheet(208/226 Pages) TOSHIBA

208 / 226 page

TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-208

2.17.2

Functions

(1) Video signal input

A low pass filter, a voltage amplifier and a condenser of about 0.1

μF are connected

between the video signal and the video signal input pin of VIN1 and VIN0 pins, that is

shown as Figure 2.17.3 the low pass filter functions to reduce noise and color burst

from the video signal, passes the amplifier and inputs the video signal to both VIN1

and VIN0 pins.

(2) Synchronous separator

This circuit is to separate the synchronous signal from the video signal. When

DACL7 to DACL0 of DACLCR are set for the synchronous separation, the sync slice

level is capable of setting. DACL7 to DACL4 set the slice level at the rising edge of the

sync signal clamped data, and DACL3 to DACL0 set the slice level at the falling edge of

the sync-tip clamped data. (Refer to section 2.17.5)

(3) Data separator

The data separator replaces the caption data piled on the video signal with the

digital signal.

When SLVL5 to SLVL0 of SLVLCR are set to get the digital signal, the Initial value

of the caption data slice level is capable of setting. (Refer to section 2.17.5)

(4) Sync-tip clamp circuit

The sync-tip level is clamped to the specified value.

(5) Pedestal clamp circuit

The video signal is set to the specified voltage with the clamp pulse generated from

the H/V timing part, which is called as a pedestal clamp.

(6) DA converter

This converter gets the DA changed slice level of the clamp circuit to the comparator.

(7) Comparator

This comparator replaces the composite video signal with the digital value while

inputting to the comparator.

(8) H timing circuit

This circuit detects the horizontal synchronous signal from C.Sync signal separated

synchornously from the video signal, and generates the clamp pulse to clamp the video

signal and provides it to the pedestal clamp circuit. In addition, the circuit detects the

change of H frequency and provides the data to the sampling clock generation part.

(9) V timing circuit

This circuit detects the horizontal synchronous signal from C.Sync signal separated

synchornously from the video signal, and provides line 21 detection signal to take out

caption signal to the slice level control part.

(10) Slice level control circuit

This circuit detects CRI (Clock run in) signal from VIDEO signal with line 21

detection signal generated at H/V timing part after slicing, and controls to the most

suitable slice level and takes out the caption data.

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