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TMP88CS38 Datasheet(PDF) 207 Page - Toshiba Semiconductor

Part # TMP88CS38
Description  8-bit single chip microcomputer
PDF  226 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP88CS38 Datasheet(HTML) 207 Page - Toshiba Semiconductor

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TMP88CS38/CM38A/CP38A
2007-09-12
88CS38-207
2.17 Data Slicer
The TMP88CS38/CM38A/CP38A contains the data slicer to decode the caption data which
multiplied during vertical flyback time of the composite video signal.
The composite video signal inputs to the data slicer circuit through P32 (VIN1) and P33
(VIN0). The caption data is decoded from the video signal. The composite video signal including
negative sync-tip inputs to VIN0 and VIN1 pins. The data slicer can comply with the copy guard
signal and special signals, and receive accurately the caption data under the condition of a weak
electrical field or a ghost.
Note:
When the data slicer is used at fc
= 16 MHz, set to “02H” in FC8CR.
When the data slicer is used at fc
= 8 MHz, set to “00H” in FC8CR. (Refer to Figure 1.4.5)
2.17.1
Configuration
Figure 2.17.1 Data Slicer
C.Sync external input mode
C.Sync signal
Composite
video
signal
Sync-tip clamp
circuit
Pedestal clamp
circuit
Com-
parator 1
H timing circuit
V timing circuit
SIFSMS1/SIFS1R
A0
A1
Z
S
Com-
parator 2
Slice level control
circuit
Sampling clock
generation
circuit
INTSLI
(to Interrupt)
SIFSR
(00FDDH)
Slicer interface
circuit
SIFDR2
SIFDR1
(00FDBH)
Data register 1
(00FDCH)
Data register 2
Slicer mode setting register 1
SIF status read register 2
(00FDFH)
SYNCINV
EXSYNC
Synchronous separator
SLVLCR
DACLCR
DA converter
DA converter
Data separator
Clamping pulse
21
LINE
VIN1
VIN0
(00FDAH)
Slice level
control register
(00FD9H)
Sync-tip slice level
setting register



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