LT7153SP datasheet(9/31 Pages) AD

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Data Sheet

LT7153SP

analog.com

Rev 0

9 of 31

Table 3. Pin Descriptions

NAME

DESCRIPTION

INTVcc

Internal 3.6V regulator output. The internal power drivers and control circuits are

powered from this voltage. Decouple this pin to power ground with a minimum of

4.7µF low ESR ceramic capacitor.

2-12

Switch node connection of external inductor. Voltage swing of SW is from a diode

voltage drop below ground to a diode voltage above PVIN.

RUN

Logic controlled RUN input. Do not leave this pin floating. Logic high activates the

step-down regulator.

AVPSEL

Use this pin to select between three different load lines; tied to GND: 0.2%, float: 1%,

INTVcc:1.5%.

PHSMD1/

ISEL

Control inputs to the phase selector and ILIM option. A high or low state on this pin, in

conjunction with the state of the PHSMD2/ILIM pin, determines the phase relationship

between SYNC and the internal oscillator and between the internal oscillator and

CLKOUT. When this pin is floated to mid rail (1/2 INTVcc), the PHSMD2/ILIM pin can be

used to select between three lower ILIM settings.

PHSMD2/

ILIM

Control inputs to the phase selector and ILIM set. When PHSMD1/ISEL is high or low,

this pin in conjunction with PHSMD1/ILIM determines the phasing between SYNC and

the internal oscillator and between the internal oscillator and CLKOUT. When

PHSMD1/ISEL is floated to mid rail (1/2 INTVcc), this pin can be used to select between

three different lower ILIM settings.

MODE

Mode select pin. Tie MODE to GND for discontinuous mode of operation. Float or tie

MODE to a voltage above 1V selects forced continuous mode.

PGOOD

Output power good with open-drain logic. PGOOD is pulled to ground when the

voltage of the FB pin is not within ±6.5% of the internal 0.5V reference.

19-27

PVIN

Power VIN. Input voltage to the on-chip power MOSFETs.

SYNC/

SPREAD

Spread spectrum select and oscillator synchronization pin. Tie SYNC/SPREAD to GND

to disable spread spectrum operation; tie to INTVcc or float to start spread spectrum.

Connect to an external clock to synchronize the system clock to the external clock and

put the part in forced continuous mode.

SVIN

Signal VIN. Filtered input voltage to the on-chip 3.6V regulator. Bypass the signal into

the SVIN pin through a 2.2Ω resistor in series with 10µF ceramic capacitor.

CLKOUT

Output clock signal for PolyPhase operation. The phase of CLKOUT with respect to

SYNC is determined by the state of PHSMD1 and PHSMD2 pins. CLKOUT’s peak-to-peak

amplitude is INTVcc to GND. Minimize the parasitic capacitance on this pin to reduce

phase errors. When RUN is low, this pin defaults high.

SGND

Ground for signal ground.

Switching frequency programming pin. Connect an external resistor from this pin to

GND to program the frequency from 400kHz to 5MHz.

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