Data Sheet

LT7153SP

analog.com

Rev 0

18 of 31

APPLICATIONS INFORMATION

A simplified LT7153SP application circuit is shown on the first page of the data sheet. External component selection

is largely driven by the target current ripple, load requirement, and switching frequency. Component selection

typically begins with the selection of the inductor L and resistor RRT. Once the inductor is chosen, select the input

capacitor, CIN, and the output capacitor, COUT. Next, select the feedback resistors to set the desired output voltage.

Finally, select the remaining optional external components for functions such as external loop compensation,

tracking/soft-start, input UVLO, and PGOOD.

Silent Switcher Architecture

The LT7153SP has integrated capacitors that allow it to operate at high switching frequencies efficiently. The internal

VIN bypass capacitors allow the SW edges to transition extremely fast, effectively reducing transition loss. The

capacitors also greatly reduce SW overshoot during top FET turn-on, which improves the robustness of the device

over time.

Programming Switching Frequency

Selection of the switching frequency is a trade-off between efficiency and component size. High frequency operation

allows the use of smaller inductors and capacitors. Operating at lower frequencies improves efficiency by reducing

internal gate charge losses but requires larger inductances and capacitances to maintain low output ripple voltage.

Connecting a resistor, RRT, from the RT pin to SGND programs the switching frequency, f

SW, from 400kHz to 5MHz

according to the following formula:

fSW(Hz) =

1e11

RRT(Ω)

The internal PLL has a synchronization range of ±30% around its programmed frequency. Therefore, during external

clock synchronization be sure that the external clock frequency is within this ±30% range of the RRT programmed

frequency.

Output Voltage Programming

Each regulator’s output voltage is set by an external resistive divider according to the following equation:

VOUT = 0.5V • (1 +

R1

R2

)

The desired output voltage is set by the appropriate selection of resistors R1 and R2, which allow the VFB pin to sense

a fraction of the output voltage, as shown in Figure 27. Choosing large values for R1 and R2 results in improved

zero/light load efficiency but may lead to undesirable noise coupling or phase margin reduction due to stray

capacitances at the VFB node. Take care to route the VFB trace away from any noise source, such as SW trace. A

feedforward compensation capacitor, CFF, can also be placed between VOUT and FB to improve transient performance.

Figure 27.Setting the Output Voltage

If the output voltage is outside the VON sense range (0.5V ~ 4V), the output voltage stays in regulation, but the

switching frequency may deviate from the programmed frequency.

FB

GND

VOUT

LT7153SP

KELVIN TO

POL GND

R1

R2

CFF