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Preliminary Technical Data

AD5422

Rev. PrE | Page 11 of 37

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD5422

AGND

SDO

AVSS

+VSENSE

FAULT

GND

LATCH

CLEAR

CLEAR SELECT

REFIN

SELECT

SCLK

SDIN

GND

RSET

VOUT

BOOST

CCOMP1

REFOUT

TOP VIEW

(Not to Scale)

DVCC

CCOMP2

I OUT

-VSENSE

AVDD

DVCC

LATCH

CLEAR SELECT

GND

FAULT

DVCC SELECT

BOOST

CCOMP1

CCOMP2

IOUT

SDO

SDIN

SCLK

CLEAR

TOP VIEW

(Not to Scale)

AD5422

CAP2

CAP1

Figure 5. TSSOP Pin Configuration

Figure 6. LFCSP Pin Configuration

Table 6. Pin Function Descriptions

TSSOP Pin No.

LFCSP Pin No.

Mnemonic

Description

14,37

AVSS

Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be

connected to 0V if output voltage range is unipolar.

DVCC

Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.

FAULT

Fault alert, This pin is asserted low when an open circuit is detected in current mode or

an over temperature is detected. Open drain output, must be connected to a pull-up

resistor.

4,12

3,15

GND

These pins must be connected to 0V.

1,10,11,19,

20,21,22,30,

31,35,38,40

No Connection.

CLEAR

SELECT

Selects the voltage output clear value, either zero-scale or mid-scale code. See Table 20

CLEAR

Active High Input. Asserting this pin will set the current output to the bottom of the

selected range or will set the voltage output to the user selected value (zero-scale or

mid-scale).

LATCH

Positive edge sensitive latch, a rising edge will parallel load the input shift register data

into the DAC register, also updating the output.

SCLK

Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This

operates at clock speeds up to 30 MHz.

SDIN

Serial Data Input. Data must be valid on the rising edge of SCLK.

SDO

Serial Data Output. Used to clock data from the serial register in daisy-chain or readback

mode. Data is clocked out on the falling edge of SCLK . See Figure 3 and Figure 4.

AGND

Ground reference pin for analog circuitry.

N/A

DGND

Ground reference pin for digital circuitry. (AGND and DGND are internally connected in

TSSOP package).

RSET

An external, precision, low drift 15k

Ω current setting resistor can be connected to this

pin to improve the IOUT temperature drift performance. Refer to Features section.

REFOUT

Internal Reference Voltage Output. REFOUT = 5 V ± 2 mV.

REFIN

External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for

specified performance.

DVCC

SELECT

This pin when connected to GND disables the internal supply and an external supply

must be connected to the DVCC pin. Leave this pin unconnected to enable the internal

supply. Refer to features section.

CCOMP1

CCOMP2

Optional compensation capacitor connection for the voltage output buffer. Connecting

a 4nF capacitor between these pins will allow the voltage output to drive up to 1µF.

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