AD5422 datasheet(31/37 Pages) AD

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Preliminary Technical Data

AD5422

Rev. PrE | Page 31 of 37

FEATURES

FAULT ALERT

The AD5422 is equipped with a FAULT pin, this is an open-

drain output allowing several AD5422 devices to be connected

together to one pull-up resistor for global fault detection. The

FAULT pin is forced active by any one of the following fault

scenarios;

The Voltage at IOUT attempts to rise above the

compliance range, due to an open-loop circuit or

insufficient power supply voltage. The IOUT current is

controlled by a PMOS transistor and internal

amplifier as shown in Figure 58. The internal circuitry

that develops the fault output avoids using a

comparator with “window limits” since this would

require an actual output error before the FAULT

output becomes active. Instead, the signal is generated

when the internal amplifier in the output stage has less

than approxiamately one volt of remaining drive

capability (when the gate of the output PMOS

transistor nearly reaches ground). Thus the FAULT

output activates slightly before the compliance limit is

reached. Since the comparison is made within the

feedback loop of the output amplifier, the output

accuracy is maintained by its open-loop gain and an

output error does not occur before the FAULT output

becomes active.

If the core temperature of the AD5422 exceeds approx.

150°C.

The OPEN CCT and OVER TEMP bits of the STATUS register

are used in conjunction with the FAULT pin to inform the user

which one of the fault conditions caused the FAULT pin to be

asserted. See Table 18 and Table 19.

VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION

Under normal operation the voltage output will sink/source

5mA and maintain specified operation. The maximum current

that the voltage output will deliver is 10mA, this is the short

circuit current.

ASYNCHRONOUS CLEAR (CLEAR)

CLEAR is an active high clear that allows the voltage output to

be cleared to either zero-scale code or mid-scale code, user-

selectable via the CLEAR SELECT pin or the CLRSEL bit of the

CONTROL register as described in Table 20. (The Clear select

feature is a logical OR function of the CLEAR SELECT pin and

the CLRSEL bit). The Current output will clear to the bottom of

its programmed range. It is necessary to maintain CLEAR high

for a minimum amount of time (see Figure 2) to complete the

operation. When the CLEAR signal is returned low, the output

remains at the cleared value until a new value is programmed.

Table 20. CLEAR SELECT Options

CLR SELECT

Output CLR Value

Unipolar Output Range

Bipolar Output Range

0 V

Mid-Scale

Negative Full-Scale

INTERNAL REFERENCE

The AD5422 contains an integrated +5V voltage reference with

initial accuracy of ±2mV max and a temperature drift

coefficient of ±10 ppm max. The reference voltage is buffered

and externally available for use elsewhere within the system. See

Figure 56 for a load regulation graph of the Integrated reference.

EXTERNAL CURRENT SETTING RESISTOR

Referring to Figure 58, R1 is an internal sense resistor as part of

the voltage to current conversion circuitry. The stability of the

output current over temperature is dependent on the stability of

the value of R1. As a method of improving the stability of the

output current over temperature an external precision 15kΩ low

drift resistor can be connected to the RSET pin of the AD5422 to

be used instead of the internal resistor R1. The external resistor

is selected via the CONTROL register. See Table 13.

VOLTAGE OUTPUT OVER-RANGE

An over-range facility is provided on the voltage output. When

enabled via the CONTROL register, the selected output range

will be over-ranged by 10%.

DIGITAL POWER SUPPLY

By default the DVCC pin accepts a power supply of 2.7V to 5.5V,

alternatively, via the DVCC SELECT pin an internal 4.5V power

supply may be output on the DVCC pin for use as a digital power

supply for other devices in the system or as a termination for

pull-up resistors. This facility offers the advantage of not having

to bring a digital supply across an isolation barrier. The internal

power supply is enabled by leaving the DVCC SELECT pin

unconnected. To disable the internal supply DVCC SELECT

should be tied to 0V.

EXTERNAL BOOST FUNCTION

The addition of an external boost transistor as shown in Figure

61 will reduce the power dissipated in the AD5422 by reducing

the current flowing in the on-chip output transistor (dividing it

by the current gain of the external circuit). A discrete NPN

transistor with a breakdown voltage, BVCEO, greater than 60V

can be used.

The external boost capability has been developed for those

users who may wish to use the AD5422 at the extremes of the

supply voltage, load current and temperature range. The boost

transistor can also be used to reduce the amount of temperature

induced drift in the part. This will minimise the temperature

induced drift of the on-chip voltage reference, which improves

drift and linearity.

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