SN888C

SLLSEI4 – SEPTEMBER 2013

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Design and Layout Considerations for Transient Protection

Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-

frequency layout techniques must be applied during PCB design.

In order for PCB design to be successful, begin with the design of the protection circuit in mind.

1. Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your

board.

2. Use Vcc and ground planes to provide low-inductance. Note that high-frequency currents follow the path of

least inductance, not the path of least impedance.

3. Design the protection components into the direction of the signal path. Do not force the transients currents to

divert from the signal path to reach the protection device.

4. Apply 100-NF to 220-nF bypass capacitors as close as possible to the VCC-pins of transceiver, UART,

controller ICs on the board.

5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to

minimize effective via-inductance.

6. Use 1-k to 10-k pull-up or pull-down resistors for enable lines to limit noise currents in these lines during

transient events.

7. Insert pulse-proof resistors into the A and B bus lines, if the TVS clamping voltage is higher than the

specified maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping

current into the transceiver and prevent it from latching up.

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While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-

oxide varistors (MOVs), which reduce the transients to a few-hundred volts of clamping voltage, and

transient blocking units (TBUs) that limit transient current to 200 mA.

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