-Vod

+Vod

Dm

VAm

VBm

DIRm

high Z

-Vid

+Vid

tFS

Rs

VAs

VBs

Uncorrected R output:

R is in phase with

wrong VID polarity

Corrected R output:

R is reversed to

wrong VID polarity

DIRs

Low due to pull-down

or actively driven

VSs

Low due to pull-down and then actively driven

Master

signals

Slave

signals

VFS

VFS

0V

0V

SN888C

SLLSEI4 – SEPTEMBER 2013

www.ti.com

Figure 12. Polarity Correction Timing Prior to a Data Transmission

Initially the slave receiver assumes that the correct bus polarity is applied to the inputs and performs no polarity

reversal. Because of the reversed polarity of the bus-failsafe voltage, the output of the slave receiver, RS, turns

low. After tFS has passed and the receiver has detected the wrong bus polarity, the internal POLCOR logic

reverses the input signal and RS turns high.

At this point, all incoming bus data with reversed polarity are polarity-corrected within the transceiver. Because

polarity correction is also applied to the transmit path, the data sent by the slave MCU are reversed by the

POLCOR logic, then fed into the driver.

The reversed data from the slave MCU are reversed again by the cross-wire fault in the bus, and the correct bus

polarity is reestablished at the master end.

This process repeats each time the device powers up and detects an incorrect bus polarity.

10

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