A

B

D

DE

R

RE

Vcc

GND

A

B

D

DE

R

RE

VS-Master

RFS

RFS

RT

(opt.)

VSM

GND

Vcc

VS-Slave

RxD

TxD

DIR

MCU

DGND

Vdd

VS-Slave

RxD

TxD

DIR

MCU

DGND

Vdd

VS-Master

Slave

node

Master

node

RT

(opt.)

SN888C

www.ti.com

SLLSEI4 – SEPTEMBER 2013

DEVICE INFORMATION

Low-Power Standby Mode

When the driver and the receiver are both disabled (DE = low and RE = high) the device enters standby mode. If

the enable inputs are in the disabled state for only a brief time (for example: less than 100 ns), the device does

not enter standby mode, preventing the SN888C device from entering standby mode during driver or receiver

enabling. Only when the enable inputs are held in the disabled state for a duration of 300 ns or more does the

device enter low-power standby mode. In this mode most internal circuitry is powered down, and the steady-state

supply current is typically less than 400 nA. When either the driver or the receiver is re-enabled, the internal

circuitry becomes active. During VCC power-up, when the device is set for both driver and receiver disabled

mode, the device may consume more than 5-µA of ICC disabled current because of capacitance charging

effects. This condition occurs only during VCC power-up.

Bus Polarity Correction

The SN888C device automatically corrects a wrong bus-signal polarity caused by a cross-wire fault. In order to

detect the bus polarity, all three of the following conditions must be met:

•

A failsafe-biasing network (commonly at the master node) must define the signal polarity of the bus.

•

A slave node must enable the receiver and disable the driver (/RE = DE = low).

•

The bus must idle for the failsafe time, tFS-max.

After the failsafe time has passed, the polarity correction is complete and applied to both the receive and transmit

channels. The status of the bus polarity latches within the transceiver and maintains for subsequent data

transmissions.

NOTE

Avoid data string durations of consecutive 0s or 1s exceeding tFS-min, which can accidently

trigger a wrong polarity correction.

Figure 11 shows a simple point-to-point data link between a master node and a slave node. Because the master

node with the failsafe biasing network determines the signal polarity on the bus, an RS-485 transceiver without

polarity correction, such as SN65HVD82, suffices. All other bus nodes, typically performing as slaves, require the

SN888C transceiver with polarity correction.

Figure 11. Point-To-Point Data Link With Cross-Wire Fault

Prior to initiating data transmission the master transceiver must idle for a time span that exceeds the maximum

failsafe time, tFS-max, of a slave transceiver. To accomplish this idle time, drive the direction control line, DIR, low.

After a time, t > tFS-max, the master begins transmitting data.

Because of the indicated cross-wire fault between master and slave, the slave node receives bus signals with

reversed polarity. Assuming the slave node has just been connected to the bus, the direction-control pin is

pulled-down during power-up, and then is actively driven low by the slave MCU. The polarity correction begins as

soon as the slave supply is established and ends after approximately 44 to 76 ms.

Copyright © 2013, Texas Instruments Incorporated

Submit Documentation Feedback

9

Product Folder Links: SN888C