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TSU6721 Datasheet(PDF) 21 Page - Texas Instruments |
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TSU6721 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 45 page  SCL SDA ST 0 1 0 0 1 0 1 0 A 1 0 0 0 0 0 1 1 A SP 0 1 0 0 1 0 1 1 A D7 D6 D5 D4 D3 D2 D1 D0 Start Slave Address W/R ACKFromSlave Sub Address ACK From Slave Auto-Inc. Slave Address W/R ACKFromSlave Stop DateByte A A ACKFromMaster D7 D6 D5 D4 D3 D2 D1 D0 DateByte NA D7 D6 D5 D4 D3 D2 D1 D0 DateByte DatafromInterrupt1Reg. DatafromInterrupt2Reg. Datafrom Int Mask1Reg. ACKFromMaster No (MessageEnds) ACKFromMaster Continued SP Stop ST Start Register Address (Interrupt1Reg) continued SDA ST 0 1 0 0 1 0 1 0 A 0 0 0 0 0 0 1 1 A SP 0 1 0 0 1 0 1 1 A D7 D6 D5 D4 D3 D2 D1 D0 Start Slave Address W/R ACKFromSlave Sub Address ACK From Slave Auto-Inc. Slave Address W/R ACKFromSlave Stop DateByte A A ACKFromMaster D7 D6 D5 D4 D3 D2 D1 D0 DateByte NA D7 D6 D5 D4 D3 D2 D1 D0 DateByte DatafromInterrupt1Reg. ACKFromMaster No ACKFromMaster(MessageEnds) Continued SP Stop ST Start Register Address (Interrupt1Reg) DatafromInterrupt1Reg. DatafromInterrupt1Reg. continued SCL SDA ST 0 1 0 0 1 0 1 0 A 1 0 0 0 0 0 1 1 A RS 0 1 0 0 1 0 1 1 A D7 D6 D5 D4 D3 D2 D1 D0 Start Slave Address W/R ACKFromSlave Sub Address ACK From Slave Auto-Inc. Slave Address W/R ACKFromSlave Re-Start DateByte A A ACKFromMaster D7 D6 D5 D4 D3 D2 D1 D0 DateByte NA D7 D6 D5 D4 D3 D2 D1 D0 DateByte DatafromInterrupt1Reg. DatafromInterrupt2Reg. Datafrom Int Mask1Reg. ACKFromMaster No ACKFromMaster(MessageEnds) SP Stop Register Address (Interrupt1Reg) continued TSU6721YFF www.ti.com SCDS345 – JUNE 2013 Figure 13. Burst Data Read from Multiple Registers – Combined Mode Figure 14. Repeated Data Read from a Single Register – Split Mode Figure 15. Burst Data Read from Multiple Registers – Split Mode Notes (Applicable to Figure 10 – Figure 15): • SDA is pulled low on Ack. from slave or Ack. from master. • Register writes always require sub-address write before first data byte. • Repeated data writes to a single register continue indefinitely until Stop or Re-Start. • Repeated data reads from a single register continue indefinitely until No Ack. from master. • Burst data writes start at the specified register address, then advance to the next register address, even to the read-only registers. For these registers, data write appears to occur, though no data are changed by the writes. After register 14h is written, writing resumes to register 01h and continues until Stop or Re-Start. • Burst data reads start at the specified register address, then advance to the next register address. Once register 14h is read, reading resumes from register 01h and continues until No Ack. from master. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links :TSU6721YFF |
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