LM8323

SNLS273A – JULY 2010 – REVISED MARCH 2013

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AC ELECTRICAL CHARACTERISTICS

(Temperature: -40°C

≤ TA ≤ +85°C)

Data sheet specification limits are specified by design, test, or statistical analysis.

Parameter

Conditions

Min

Typ

Max

Units

System Clock Frequency

Internal RC

21

MHz

System Clock Period (mclk)

1.62V

≤ VCC ≤ 1.98V

48

ns

Processing and Command Execution Cycle (tC)

1.62V

≤ VCC ≤ 1.98V

0.5

μs

System Clock, Processing and Command Execution

7

%

Cycle Variation

General-Purpose I/O (GPIO)

Output Rise Time(1)

CLOAD = 50 pF

15

ns

Output Fall Time(1)

15

ns

ACCESS.bus Input Signals

Bus Free Time Between Stop and Start Condition

16

mclk

(tBUFi) (1)

SCL Setup Time (tCSTOsi) (1)

Before Stop Condition

8

mclk

SCL Hold Time (tCSTRhi) (1)

After Start Condition

8

mclk

SCL Setup Time (tCSTRsi) (1)

Before Start Condition

8

mclk

Data High Setup Time (tDHCsi) (1) (2)

Before SCL Rising Edge (RE)

2

mclk

Data Low Setup Time (tDLCsi) (1) (2)

Before SCL RE

2

mclk

SCL Low Time (tSCLlowi) (1)

After SCL Falling Edge (FE)

12

mclk

SCL High Time (tSCLhighi) (1) (2)

After SCL RE

12

mclk

SDA Hold Time (tSDAhi) (1)

After SCL FE

0

mclk

SDA Setup Time (tSDAsi) (1) (2)

Before SCL RE

2

mclk

ACCESS.bus Output Signals

SCL Hold Time (tSDAho) (1)

After SCL FE

7

mclk

(1)

Specified by design, not tested.

(2)

The ACCESS.bus interface implements and meets the timing necessary for interface to the I2C and SMBus protocol at logic levels. The

bus drivers are designed with open-drain output for bidirectional operation. Due to System Clock (mclk) Variation, this specification may

not meet the AC timing and current/voltage drive requirements of the full bus specifications.

Figure 21. ACB Start and Stop Condition Timing

40

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