LM8323 datasheet(7/46 Pages) TI2

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LM8323

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SNLS273A – JULY 2010 – REVISED MARCH 2013

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Internal PWM Clock — The internal PWM clock is a fixed scaled down clock (÷ 64) of the Processing and

Command Execution Clock. This clock is close to 32 kHz which is in a good range to source the PWM

function block as an alternative to an external clock source.

•

External 32.768 kHz Clock — driven into the SLOWCLK input. May be used internally as the timebase for

the PWM and driven on the SLOWCLKOUT output.

•

External 32.768 kHz Crystal — connected across the XTAL_IN and XTAL_OUT pins (XTAL_IN is an

alternate function of the SLOWCLK pin). May be used internally as the timebase for the PWM and driven on

the SLOWCLKOUT output.

Figure 3. Clock Architecture

INTERNAL EXECUTION CYCLE

The Processing - and Command - execution clock is about 2MHz. This clock is stopped in Halt mode, which only

occurs under control of the LM8323. However, the host can set the period of inactivity which causes the device

to enter Halt mode.

Exit from Halt mode can be triggered by any of these events:

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Occurrence of a key-press or key-release event.

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A Start condition driven by the host on the ACCESS.bus interface.

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Any change to the rotary encoder counter value (if the interface is enabled).

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Assertion of the RESET input.

After reset, the default timebase for the PWM outputs is the internal execution clock divided by 64.

BUFFERED CLOCK

The timebase for the PWM comes from any of three sources:

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Prescaled internal Execution clock.

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External 32.768 kHz clock received on the SLOWCLK input.

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On-chip oscillator with an external crystal connected across XTAL_IN and XTAL_OUT.

Any of these sources may be buffered and driven on the SLOWCLKOUT output. The clock buffer is enabled with

the WRITE_CLOCK command.

If XTAL_IN is not used it must be terminated to VCC or GND.

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