LM8323 datasheet(8/46 Pages) TI2

8 / 46 page

LM8323

SNLS273A – JULY 2010 – REVISED MARCH 2013

www.ti.com

CLOCK CONFIGURATION

Table 1 shows the clock configurations available by loading the clock configuration register with the

WRITE_CLOCK command. The WRITE_CLOCK command must be issued only once during system initialization.

This command is used to override the default settings.

Table 1. Clock Configuration Register

SLOWCLKOUT

SLOWCLKEN

RCPWM

Bit

Value

Description

Disable SLOWCLKOUT buffer.

SLOWCLKOUT

Enable SLOWCLKOUT buffer.

External 32.768 kHz crystal is installed between the XTAL_IN and XTAL_OUT pins.

SLOWCLKEN

External 32.768 kHz clock is received on the SLOWCLK pin, or no 32.768 kHz clock is required.

On-chip RC clock divided by 64 drives the PWM and clock buffer.

Reserved

RCPWM

Reserved

External 32.768 kHz clock or crystal drives the PWM and clock buffer.

The SLOWCLKOUT signal is an alternate function of the pin used for the KP-Y8 scanning output and the

GPIO_03 port. If the SLOWCLKOUT function is enabled, these other functions of the pin are unavailable.

RESET

The LM8323 may be reset by either an external reset, RESET command, or an internally generated power-on

reset (POR) signal. The RESET input must not be allowed to float. If the external RESET input is not used, it

must be connected to VCC, either directly or through a pull-up resistor.

EXTERNAL RESET

The device enters a reset state immediately when the RESET input is driven low. RESET must be held low for a

minimum of 700 ns to ensure a valid reset. If RESET is asserted at power-on, it must be held low until VCC rises

above the minimum operating voltage (1.62V). If an RC circuit is used to drive RESET, it must have a time

constant 5 times (5×) greater than the VCC rise time to this level.

When RESET goes low, the I/O ports are initialized immediately, any observed delay being only propagation

delay. When the RESET pin goes high, the LM8323 comes out of the reset state within about 1400 ns.

POWER-ON RESET (POR)

The POR circuit is always enabled. When VCC rises above the POR threshold voltage VPOR (about 1.2–1.5V), an

on-chip reset signal is asserted. The VCC rise time must be greater than 20 µs and less than 10 ms, otherwise

the on-chip reset signal may deassert before VCC reaches the minimum operating voltage. While VCC is below

VPOR, the LM8323 is held in reset and a timer clocked by the on-chip RC clock is preset with 0xFF (256 clock

cycles). When VCC reaches a value greater than VPOR, the timer starts counting down. When it underflows, the

on-chip reset signal is deasserted and the LM8323 begins operation.

PIN CONFIGURATION AFTER RESET

Table 2 shows the pin configuration after reset.

Submit Documentation Feedback

Product Folder Links: LM8323

LM8323 Datasheet(PDF) 8 Page - Texas Instruments

LM8323 Datasheet(HTML) 8 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL