LM8323 datasheet(10/46 Pages) TI2

10 / 46 page

LM8323

SNLS273A – JULY 2010 – REVISED MARCH 2013

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NOTE

When FW6 version devices receive a RESET command the IRQ line is set high and held

high for 60 ms and then pulled low to show the device was successfully reset and is ready

to be used.

CONFIGURATION INPUTS

The states sampled from the CONFIG_1 and CONFIG_2 inputs during reset select the ACCESS.bus address

used by the LM8323, as shown in Table 3. The address occupies the high seven bits of the first byte of a bus

transaction, with the LSB (shown as X below) indicating the direction of transfer.

Table 3. Bus Address Selection

CONFIG_1

CONFIG_2

Bus Address

1000 010X

1000 011X

1000 100X

1000 101X

When these pins are used as GPIO ports, the design must ensure that they have the desired states during reset.

For example, a 100-k

Ω resistor to ground can impose a logic 0 during reset without interfering with normal

operation as a GPIO port.

INITIALIZATION

The LM8323 waits for a WRITE_CFG command from the host. During this time, IRQ is asserted to request

service from the host. Figure 4 describes the behavior of the LM8323 following reset.

Figure 4. LM8323 Initialization Behavior

Figure 5 shows the timing of IRQ relative to a RESET or POR event and the WRITE_CFG command. 100 µs

after a RESET or POR event, IRQ is asserted and any READ_INT command will return an interrupt code with

the NOINIT bit set. 90 µs after a WRITE_CFG command is received, IRQ is deasserted.

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LM8323 Datasheet(PDF) 10 Page - Texas Instruments