LM96063 datasheet(28/46 Pages) TI2

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LM96063

SNIS149B – NOVEMBER 2011 – REVISED MARCH 2013

www.ti.com

Configuration Register

Address

Read/

POR

Bits

Name

Description

Hex

Write

Value

03 (09)HEX CONFIGURATION REGISTER

ALERT Mask

0: ALERT interrupts are enabled.

ALTMSK

1: ALERT interrupts are masked, and the ALERT pin is always in a high

impedance (open) state.

Standby

0: the LM96063 is in operational mode, converting, comparing, and updating the

PWM output continuously.

1: the LM96063 enters a low power standby mode.

STBY

R/W

In standby, continuous conversions are stopped, but a conversion/comparison

cycle may be initiated by writing any value to register 0x0F the One-shot Register.

Operation of the PWM output in standby depends on the setting of bit 5 in this

PWM Disable in Standby

0: the LM96063’s PWM output continues to output the current fan control signal

PWMDIS

while in STANDBY.

03 (09)

1: the PWM output is disabled (as defined by the PWM polarity bit) while in

STANDBY.

4:3

[Reserved]

This bit is unused and always read as 0.

TACH Enable

TCHEN

0: disables the TACH input

1: enables the TACH input

T_CRIT Limit Override

TCRITOV

0: locks the T_CRIT limit for the remote diode, POR setting is nominally 110°C

1: unlocks the T_CRIT limit and allows it to be reprogrammed multiple times

R/W

RDTS Fault Queue

0: an ALERT will be generated if any Remote Diode conversion result is above the

Remote High Set Point or below the Remote Low Setpoint.

FLTQUE

1: an ALERT will be generated only if three consecutive Remote Diode

conversions are above the Remote High Set Point or below the Remote Low

Setpoint.

Tachometer Count and Limit Registers

Address

Read/

POR

Bits

Name

Description

Hex

Write

Value

47HEX TACHOMETER COUNT (MSB) and 46HEX TACHOMETER COUNT (LSB) REGISTERS (16 bits: Read LSB first to lock MSB and

ensure MSB and LSB are from the same reading)

7:0

N/A

TAC13:TAC6

Tachometer Count (MSB and LSB)

These registers contain the current 16-bit Tachometer Count, representing the

period of time between tach pulses.

7:2

N/A

TAC5:TAC0

Note that the 16-bit tachometer MSB and LSB register addresses are in reverse

order from the 16 bit temperature readings.

Tachometer Edge Programming

Bits

Edges Used

Tach_Count_Multiple

00:

Reserved - do not use

01:

1:0

TEDGE1:TEDGE0

10:

11:

Note: If PWM_Clock_Select = 360 kHz, then Tach_Count_Multiple = 1 regardless

of the setting of these bits.

49HEX TACHOMETER LIMIT (MSB) and 48HEX TACHOMETER LIMIT (LSB) REGISTERS

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