VIH

VIL

SMBCLK

P

S

VIH

VIL

SMBDAT

tBUF

tHD;STA

tLOW

tR

tHD;DAT

tHIGH

tF

tSU;DAT

tSU;STA

tSU;STO

P

S

LM96063

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SNIS149B – NOVEMBER 2011 – REVISED MARCH 2013

SMBus Digital Switching Characteristics

Unless otherwise noted, these specifications apply for VDD = +3.0 VDC to +3.6 VDC, CL (load capacitance) on output lines =

80 pF. Boldface limits apply for TA = TJ; TMIN ≤ TA ≤ TMAX; all other limits TA = TJ = +25°C, unless otherwise noted. The

switching characteristics of the LM96063 fully meet or exceed the published specifications of the SMBus version 2.0. The

following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM96063. They

adhere to but are not necessarily the same as the SMBus bus specifications.

Limits

Units

Parameter

Test Conditions

(1)

(Limit)

10

kHz (min)

fSMB

SMBus Clock Frequency

100

kHz (max)

tLOW

SMBus Clock Low Time

From VIN(0) max to VIN(0) max

4.7

µs (min)

From VIN(1) min to VIN(1) min

4.0

µs (min)

tHIGH

SMBus Clock High Time

50

µs (max)

tR

SMBus Rise Time

(2)

1

µs (max)

tF

SMBus Fall Time

(3)

0.3

µs (max)

tOF

Output Fall Time

CL = 400 pF, IO = 3 mA

250

ns (max)

SMBDAT and SMBCLK Time Low for Reset of

25

ms (min)

tTIMEOUT

Serial Interface See (4)

35

ms (max)

tSU:DAT

Data In Setup Time to SMBCLK High

250

ns (min)

300

ns (min)

tHD:DAT

Data Out Hold Time after SMBCLK Low

1075

ns (max)

Hold Time after (Repeated) Start Condition. After

tHD:STA

4.0

µs (min)

this period the first clock is generated.

tSU:STO

Stop Condition SMBCLK High to SMBDAT Low

100

ns (min)

(Stop Condition Setup)

SMBus Repeated Start-Condition Setup Time,

tSU:STA

4.7

µs (min)

SMBCLK High to SMBDAT Low

SMBus Free Time between Stop and Start

tBUF

4.7

µs (min)

Conditions

(1)

Limits are specified to AOQL (Average Outgoing Quality Level).

(2)

The output rise time is measured from (VIL max - 0.15 V) to (VIH min + 0.15 V).

(3)

The output fall time is measured from (VIH min + 0.15 V) to (VIL max - 0.15 V).

(4)

Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM96063’s SMBus state machine,

therefore setting SMBDAT and SMBCLK pins to a high impedance state.

Figure 2. SMBus Timing Diagram for SMBCLK and SMBDAT Signals

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