IN

GND

EN

(1)

OUT

FB

BYPASS

Input Plane

Input Ground

Output Ground

Output Plane

NR and FB

Ground

Denotes via

18

TPS791

SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018

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Copyright © 2001–2018, Texas Instruments Incorporated

9 Power Supply Recommendations

This device is designed to operate from an input voltage supply range from 2.7 V to 5.5 V. The input voltage

range must provide adequate headroom in order for the device to have a regulated output. This input supply

must be well-regulated and stable. A 0.1-µF input capacitor is required for stability; if the input supply is noisy,

additional input capacitors with low ESR can help improve the output noise performance.

10 Layout

10.1 Layout Guidelines

Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing

currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade

the power-supply performance. To help eliminate these problems, bypass the IN pin to ground with a low ESR

ceramic bypass capacitor with an X5R or X7R dielectric.

Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized to maximize

performance and ensure stability. Every capacitor (CIN, COUT, CBYPASS, and C1) must be placed as close as

possible to the device and on the same side of the PCB as the regulator itself.

Do not place any capacitors on the opposite side of the PCB from where the regulator is installed. The use of

vias and long traces is strongly discouraged because these circuits can impact system performance negatively,

and even cause instability.

10.1.1 Board Layout Recommendation to Improve PSRR and Noise Performance

To improve ac measurements such as PSRR, output noise, and transient response, TI recommends that the

board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the

ground pin of the device. In addition, connect the ground connection for the bypass capacitor directly to the

ground pin of the device.

10.2 Layout Example

(1)

The EN pin is active low.

Figure 38. Layout Example (6-Pin DBV Package)