6.4 Thermal Information

THERMAL METRIC (1)

TPS3813xxx

UNIT

DBV (SOT-23)

6 PINS

RθJA

Junction-to-ambient thermal resistance

208.5

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

123.3

°C/W

RθJB

Junction-to-board thermal resistance

37.2

°C/W

ψJT

Junction-to-top characterization parameter

14.6

°C/W

ψJB

Junction-to-board characterization parameter

36.3

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

n/a

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Over recommended operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

VOL

Low-level output voltage

VDD = 2V to 6V, IOL = 500µA

0.2

V

VDD = 3.3V IOL = 2mA

0.4

VDD = 6V, IOL = mA

0.4

VPOR

Power up reset voltage (1)

VDD ≥ 1.1V, IOL = 50µA

0.2

V

VIT

Negative-going input threshold

voltage (2)

TPS3813J25

TA = –40°C to +85°C

2.2

2.25

2.3

V

TPS3813L30

2.58

2.64

2.7

TPS3813K33

2.87

2.93

3

TPS3813I50

4.45

4.55

4.65

VHYS

Hysteresis

TPS3813J25

30

mV

TPS3813L30

35

TPS3813K33

40

TPS3813I50

60

IIH

High-level input current

WDI, WDR

WDI = VDD = 6V, WDR = VDD = 6V

–25

25

nA

WDT

WDT = VDD = 6V, VDD > VIT, RESET = High

–100

100

IIL

Low-level input current

WDI, WDR

WDI = 0V, WDR = 0V, VDD = 6V

–25

25

WDT

WDT = 0V, VDD > VIT, RESET = High

–100

100

IOH

High-level output current

VDD = VIT + 0.2V, VOH = VDD

25

nA

IDD

Supply current

VDD = 2V output unconnected

9

13

µA

VDD = 5V output unconnected

20

25

Ci

Input capacitance

VI = 0V to VDD

5

pF

(1)

The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15µs/V.

(2)

To provide best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1µF) must be placed near to the supply terminals.

6.6 Timing Requirements

At RL = 1MΩ, CL = 50pF, and TA = –40°C to +85°C.

MIN

TYP

MAX

UNIT

tGI_VIT Glitch immunity VIT (Pulse width at VDD)

VDD = VIT + 0.2V, VDD = VIT – 0.2V

3

µs

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TPS3813

SLVS331J – DECEMBER 2000 – REVISED AUGUST 2024

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