7 Detailed Description

7.1 Overview

The TPS3813xxx family of supervisory circuits provide circuit initialization and timing supervision signals. During

power on, RESET is asserted (low) when the supply voltage (VDD) increases above 1.1V. Thereafter, the

supervisory circuit monitors VDD and keeps RESET low as long as VDD remains below the threshold voltage

(VIT). Once VDD increases above VIT, an internal timer delays the deassertion of the output to allow for a proper

system reset before RESET transitions to a high state. The delay time (td) is 25ms typical and starts after VDD

rises above the VIT. When the supply voltage drops below VIT, the output transitions low again. All the devices of

this family have a fixed threshold voltage set by an internal voltage divider.

The TPS3813xxx family incorporates a so-called window-watchdog timer, which has a programmable delay

and window ratio. The supervised processor must trigger the WDI pin of the TPS3813xxx within the user-

programmable window to keep RESET from asserting. The upper limit of the watchdog time-out can be set by

either connecting WDT to GND, VDD, or using an external capacitor. The lower limit and thus the window ratio is

set by connecting WDR to GND or VDD.

7.2 Functional Block Diagram

RESET

WDT

_

+

Rising Edge

Detection

Watchdog

Ratio

Detection

Reset Logic

and Timer

Bandgap

Voltage

Reference

Oscillator

Detection

Circuit

WDI

WDR

GND

VDD

Power t o c ircuitry

GND

R2

R1

GND

GND

Copyright © 2016, Texas Instruments Incorporated

7.3 Feature Description

The TPS3813xxx family incorporates both a voltage supervisor and a window-watchdog timer into a single

device. The device monitors the input voltage and the supervised processor must trigger the WDI pin of the

TPS3813xxx within the user-programmable window to keep RESET from asserting.

TPS3813

SLVS331J – DECEMBER 2000 – REVISED AUGUST 2024

www.ti.com

8

Submit Document Feedback

Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TPS3813