7.3.2 User-Programmable Watchdog Timer (WDI)

The TPS3813xxx family of devices have a watchdog timer that must be periodically triggered by either a positive

or negative transition at the WDI pin to avoid a reset signal being issued. When the supervising system fails to

retrigger the watchdog circuit within the time-out interval, tt(out), RESET becomes asserts for the time period td.

This event also reinitializes the watchdog timer. After the reset of the supervisor is released, the lower boundary

of the first WDI window is disabled. After the first WDI low-to-high transition is detected, the lower boundary

function of the window is enabled. All further WDI pulses must fit into the configured window frame.

Both the upper and lower boundary of the window can be adjusted by the user. See Section 7.5 for more details

on how to set the upper and lower boundaries of the window.

7.3.3 RESET Output

RESET remains high (deasserted) as long as VDD is above the threshold voltage (VIT) and the user-programable

watchdog timer criteria are met. If VDD falls below the VIT or if WDI is not triggered within the appropriate window,

then RESET is asserted, driving the RESET pin to a low impedance.

When VDD is once again above VIT, a delay circuit is enabled that holds RESET low for a specified reset delay

period (td) which is 25ms typical. When the reset delay has elapsed, the RESET pin goes to a high-impedance

state and uses a pullup resistor to hold RESET high. Connect the pullup resistor to the proper voltage rail to

enable the outputs to be connected to other devices at the correct interface voltage level. RESET can be pulled

up to any voltage up to 6V, independent of the device supply voltage. To ensure proper voltage levels, give some

consideration when choosing the pullup resistor value and consider the required low-level output voltage (VOL),

the output capacitive loading, and the output leakage current.

7.4 Device Functional Modes

Table 7-1 summarizes the various functional modes of the device.

Table 7-1. TPS3813xxx Function/Truth Table

VDD

WDI

RESET

VDD < VPOR

—

Undefined

VPOR < VDD < VIT

—

L

VDD > VIT

Outside window

L

VDD > VIT

Inside window

H

7.4.1 Normal Operation (VDD > VIT)

When VDD is greater than VIT, the RESET signal is determined by the last WDI pulse.

• WDI pulse inside window: as long as pulses occur within the user-programmable window, the RESET signal

remains high.

• WDI pulse outside window: if a pulse occurs outside the user-programmable window or not at all, the RESET

signal goes low.

7.4.2 Above Power-On Reset But Less Than Threshold (VPOR < VDD < VIT)

When the voltage on VDD is less than the VIT voltage, and greater than the power-on reset voltage (VPOR), the

RESET signal is asserted regardless of the WDI signal.

7.4.3 Below Power-On Reset (VDD < VPOR)

When the voltage on VDD is lower than VPOR, the device does not have enough voltage to internally pull the

asserted output low, and RESET is undefined and must not be relied upon for proper device function.

TPS3813

SLVS331J – DECEMBER 2000 – REVISED AUGUST 2024

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