7.3.1 Input Voltage (VDD)

VDD pin is monitored by the internal comparator with integrated reference to indicate when VDD falls below the

fixed threshold voltage. VDD also functions as the supply for the following:

• Internal bandgap (reference voltage)

• Internal regulator

• State machine

• Buffers

• Other control logic blocks

Good design practice involves placing a 0.1µF to 1µF bypass capacitor at VDD input for noisy applications and

to make sure enough charge is available for the device to power up correctly. The reset output is undefined

when VDD is below VPOR.

7.3.1.1 VDD Hysteresis

The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDD

pin falls below the falling voltage threshold VIT, the output reset is asserted. When the voltage at the VDD pin

rises above the rising voltage threshold (VIT+ = VIT + VHYS), the output reset is deasserted after tD reset time

delay.

7.3.1.2 VDD Glitch Immunity

These devices are immune to quick voltage transient or excursion on VDD. Sensitivity to transients depends on

both pulse duration (tGI_VIT) found in Section 6.6 and transient overdrive. Overdrive is defined by how much VDD

exceeds the specified threshold. Threshold overdrive is calculated as a percent of the threshold in question, as

shown in Equation 1.

Overdrive = | ((VDD / VIT) – 1) × 100% |

(1)

where

• VIT = VIT- is the threshold voltage

• VIT+ = VIT + VHYS is the rising threshold voltage

• VDD is the input voltage crossing VIT

Overdrive

Pulse

Duration

VDD

V

IT-

V

IT+

Figure 7-1. Overdrive Versus Pulse Duration

TPS3813xxx devices have built-in glitch immunity (tGI_VIT) as shown in Section 6.6 . Figure 7-1 shows that VDD

must fall below VIT for tGI_VIT, otherwise the faling transistion is ignored. When VDD falls below VIT for tGI_VIT,

RESET transitions low to indicate a fault condition after the propagation delay high-to-low (tPHL). When VDD

rises above VIT+ = VIT + VHYS, RESET deasserts to a logic high indicating there is no more fault condition only if

VDD remains above VIT+ for longer than the reset delay (tD).

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TPS3813

SLVS331J – DECEMBER 2000 – REVISED AUGUST 2024

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