Electronic Components Datasheet Search
  English  ▼

X  

DIX4192 Datasheet(PDF) 16 Page - Texas Instruments

Part # DIX4192
Description  DIX4192 Integrated Digital Audio Interface Receiver and Transmitter
PDF  71 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DIX4192 Datasheet(HTML) 16 Page - Texas Instruments

Back Button DIX4192 Datasheet HTML 12Page - Texas Instruments DIX4192 Datasheet HTML 13Page - Texas Instruments DIX4192 Datasheet HTML 14Page - Texas Instruments DIX4192 Datasheet HTML 15Page - Texas Instruments DIX4192 Datasheet HTML 16Page - Texas Instruments DIX4192 Datasheet HTML 17Page - Texas Instruments DIX4192 Datasheet HTML 18Page - Texas Instruments DIX4192 Datasheet HTML 19Page - Texas Instruments DIX4192 Datasheet HTML 20Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 71 page
background image
X
Channel1
Y
Channel2
Channel1
Z
Y
Channel2
X
Channel1
Y
Channel2
Frame 191
Frame 0
Frame 1
BlockStart
OneSubFrame
Bits: 0
3 4
7 8
27 28 29 30 31
MSB
V U C P
Preamble
AudioData
Audioor
AuxData
ValidityBit
Use D
r
ata
Channel Status Data
P rit
a y Bit
16
DIX4192
SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016
www.ti.com
Product Folder Links: DIX4192
Submit Documentation Feedback
Copyright © 2006–2016, Texas Instruments Incorporated
Feature Description (continued)
For AES3 transmission, data is encoded into frames, with each frame containing two subframes of audio and
status data, corresponding to audio Channels 1 and 2 (or Left and Right, respectively, for stereophonic audio).
Figure 9 shows the AES3 frame and subframe formatting. Each subframe includes four bits for the preamble, up
to 24 bits for audio and/or auxiliary data, one bit indicating data validity (V), one bit for channel status data (C),
one bit for user data (U), and one bit for setting parity (P).
The 4-bit preamble is used for synchronization and identification of blocks and subframes. The X and Y preamble
codes are used to identify the start of the Channel 1 and Channel 2 subframes, as shown in Figure 9. However,
the X preamble for the first subframe of every 192 frames is replaced by the Z preamble, which identifies the
start of a new block of channel status and user data.
Figure 9. AES3 Frame and Subframe Encoding
One block is comprised of 192 frames of data. This format translates to 192 bits each for channel status and
user data for each channel. The 192 bits are organized into 24 data bytes, which are defined by the AES3-2003
and consumer standards documents. The AES18 standard defines recommended usage and formatting of the
user data bits, while consumer applications may use the user data for other purposes. The DIX4192 also
includes block-sized transmitter and receiver channel status and user data buffers, which have 24 bytes each for
the channel status and user data assigned to audio Channels 1 and 2. Refer to Channel Status and User Data
Buffer Maps for the organization of the buffered channel status and user data for the receiver and transmitter
functions.
The audio data for Channel 1 and Channel 2 may be up to 24 bits in length, and occupies bits 4 through 27 of
the corresponding subframe. Bit 4 is the LSB while bit 27 is the MSB. If only 20 bits are required for audio data,
then bits 8 through 27 are used for audio data, while bits 4 though 7 are used for auxiliary data bits.
The validity (V) bit indicates whether or not the audio sample word being transmitted is suitable for digital-to-
analog (D/A) conversion or further digital processing at the receiver end of the connection. If the validity bit is 0,
then the audio sample is suitable for conversion or additional processing. If the validity bit is 1, then the audio
sample is not suitable for conversion or additional processing.
The parity (P) bit is set to either a 0 or 1, such that bits 4 through 31 carry an even number of ones and zeros for
even parity. The DIT block in the DIX4192 automatically manages the parity bit, setting it to a 0 or 1 as required.
The DIR block checks the parity of bits 4 though 31 and generates a parity error if odd parity is detected.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com