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DIX4192 Datasheet(PDF) 60 Page - Texas Instruments |
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DIX4192 Datasheet(HTML) 60 Page - Texas Instruments |
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60 / 71 page ![]() 10 F 0.1 F Top Layer Ground Pour and PowerPad Top Layer Signal Traces Pad to top layer ground pour It is recommended to place a top layer ground pour for shielding around PCM9211 and connect to lower main PCB ground plane by multiple vias DIX4192 Series resistors between 50 -100 Q }v PCM ports can reduce reflections if necessary 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 +1. 8V 0.1 F 10 µF VIO +3. 3V 0.1 F 10 F 0.1 F SYNC BLS AESO UT VDD3 3 TX+ TX- DGND2 GPO4 GPO3 GPO2 GPO1 MCLK RX1+ RX1- RX2+ RX2- RX3+ RX3- RX4+ RX4- VCC AGND LOCK RXCKO Port B PCM Input and Output Differential Line Inputs Control Interface GPO to Host 10 F +3. 3V Port A PCM Input and Output VIO INT pin must be pulled up to VIO through 10k Q Œ •]•š}Œ 10 N Ÿ 60 DIX4192 SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: DIX4192 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated 12 Layout 12.1 Layout Guidelines TI recommends to use one ground plane for the DIX4192. While using one ground plane, it is best to ensure that analog and digital circuitry be sufficiently partitioned on the PCB so that analog and digital return currents do not cross. • Decoupling capacitors must be placed as close to power pins as possible (VCC, VDD33, VDD18, VIO). • Further guidelines can be found in Layout Example. 12.2 Layout Example Figure 85. DIX4192 Board Layout |
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