DIX4192 datasheet(14/71 Pages) TI2

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Master

Clock

Source

Master

Mo e

Clock

Generation

Serial

Input

Serial

Output

MC K

RXCKI

RXCKO

Audio Data

InternalClocks

OUTS[1:0]

MU E

F T[1:

M/S

DIV1:

[ 0]

CLK1:

[ 0]

SDN

I A (pin39)or SDINB(pin4 )

LRCKA (pin3 )or

LRCKB( i 47)

p n

BCKA(pin37)orBCKB(pin48)

SDOUTA (pin40)or SDOUTB(pin45)

Daa

Source

PortA

PortB

DIR

DIX4192

SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

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Feature Description (continued)

9.3.3 Audio Serial Port Operation

The DIX4192 includes two audio serial ports, Port A and Port B. Both ports are 4-wire synchronous serial

interfaces, supporting simultaneous input and output operation. Because each port has only one pair of left or

right word and bit clocks, the input and output sampling rates are identical. A simplified block diagram is shown in

Figure 7.

The audio serial ports may be operated at sampling rates up to 216 kHz, and support audio data word lengths up

to 24 bits. Philips I2S, Left-Justified, and Right-Justified serial data formats are supported. Refer to Figure 8.

The left or right word clock (LRCKA or LRCKB) and the bit clock (BCKA or BCKB) may be configured for either

Master or Slave mode operation. In Master mode, these clocks are outputs, derived from the selected master

clock source using internal clock dividers. The master clock source may be 128, 256, 384, or 512 times the audio

input/output sampling rate, with the clock divider being selected using control register bits for each port. In Slave

mode the left or right word and bit clocks are inputs, and are sourced from an external audio device acting as the

serial bus master.

The LRCKA or LRCKB clocks operate at the input and output sampling rate, fS. The BCKA and BCKB clock rates

are fixed at 64 times the left or right word clock rate in Master mode. For Slave mode, the minimum BCKA and

BCKB clock rate is determined by the audio data word length multiplied by two, because there are two audio

data channels per left or right word clock period. For example, if the audio data word length is 24 bits, the bit

clock rate must be at least 48 times the left or right word clock rate, allowing one bit clock period for each data bit

in the serial bit stream.

Serial audio data is clocked into the port on the rising edge of the bit clock, while data is clocked out of the port

on the falling edge of the bit clock. Refer to the Audio Serial Ports section of the Electrical Characteristics table

for parametric information and Figure 1 for a timing diagram related to audio serial port operation.

The audio serial ports are configured using control registers 0x03 through 0x06. Refer to Control Registers for

descriptions of the control register bits.

Figure 7. Audio Serial Port Block Diagram

DIX4192 Datasheet(PDF) 14 Page - Texas Instruments

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