 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DIX4192 Datasheet(PDF) 42 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
DIX4192 Datasheet(HTML) 42 Page - Texas Instruments |
|
|
42 / 71 page  42 DIX4192 SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: DIX4192 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Figure 50. Register 1B: General-Purpose Output 1 (GPO1) Control Register 7 (MSB) 6 5 4 3 2 1 0 (LSB) 0 0 0 0 GPO13 GPO12 GPO11 GPO10 Table 29. Register 1B: General-Purpose Output 1 (GPO1) Control Register Field Descriptions GPO[13:10] General-Purpose Output 1 (GPO1) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO1. GPO13 GPO12 GPO11 GPO10 GPO1 Function 0 0 0 0 GPO1 is forced low (default) 0 0 0 1 GPO1 is forced high 0 0 1 0 Reserved 0 0 1 1 Transmitter interrupt, active low 0 1 0 0 Receiver interrupt, active low 0 1 0 1 Receiver 50/15-μs pre-emphasis, active low 0 1 1 0 Receiver non-audio data, active high 0 1 1 1 Receiver non-valid data, active high 1 0 0 0 Receiver channel status bit 1 0 0 1 Receiver user data bit 1 0 1 0 Receiver block start clock 1 0 1 1 Receiver COPY bit (0 = copyright asserted, 1 = copyright not asserted) 1 1 0 0 Receiver L-bit (0 = first generation or higher, 1 = original) 1 1 0 1 Receiver parity error, active high 1 1 1 0 Receiver internal sync clock 1 1 1 1 Transmitter internal sync clock Figure 51. Register 1C: General-Purpose Output 2 (GPO2) Control Register 7 (MSB) 6 5 4 3 2 1 0 (LSB) 0 0 0 0 GPO23 GPO22 GPO21 GPO20 Table 30. Register 1C: General-Purpose Output 2 (GPO2) Control Register Field Descriptions GPO[23:20] General-Purpose Output 2 (GPO2) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO2. GPO23 GPO22 GPO21 GPO20 GPO2 Function 0 0 0 0 GPO2 is forced low (default) 0 0 0 1 GPO2 is forced high 0 0 1 0 Reserved 0 0 1 1 Transmitter interrupt, active low 0 1 0 0 Receiver interrupt, active low 0 1 0 1 Receiver 50/15-μs pre-emphasis, active low 0 1 1 0 Receiver non-audio data, active high 0 1 1 1 Receiver non-valid data, active high 1 0 0 0 Receiver channel status bit 1 0 0 1 Receiver user data bit 1 0 1 0 Receiver block start clock 1 0 1 1 Receiver COPY bit (0 = copyright asserted, 1 = copyright not asserted) 1 1 0 0 Receiver L-bit (0 = first generation or higher, 1 = original) 1 1 0 1 Receiver parity error, active high 1 1 1 0 Receiver internal sync clock 1 1 1 1 Transmitter internal sync clock |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
