DIX4192 datasheet(18/71 Pages) TI2

18 / 71 page

MCLK

RXCKO

UserAccess

(UA)Buffers

TransmitterAccess

(TA)Buffers

Channel

Status

User

Data

FromReceiver

Access(RA) Buffer

FromReceiver

Access(RA) Buffer

To/From SPIorI C

HostInterface

To/From SPIorI C

HostInterface

TXCLK

TXCUS[1:0] TXBTD

TXIS[1:0]

BLS(pin35)

SYNC(pin36)

AE 3

Encoder

AESMUX

LDMUX

AESOFF

TXOFF

From

Bypass

Multiplexer

Output

TX+(pin32)

TX (pin31)

AESOUT

(pin34)

Master

Clock

Source

Daa

Source

Channel

Status

User

Daa

TXMUTE

BL M

PortA

PortB

DIR

TXDIV[1:0]

DIX4192

SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: DIX4192

Submit Documentation Feedback

Feature Description (continued)

The Parity (P) bit will always be generated by the AES3 encoder internal parity generator logic, such that bits 4

through 31 of the AES3-encoded subframe are even parity.

The AES3 encoder output is connected to the output line driver and CMOS buffer source multiplexers. As shown

in Figure 11, the source multiplexers allow the line driver or buffer to be driven by the AES3-encoded data from

the DIT, or by the bypass multiplexer, which is associated with the outputs of the four differential input line

receivers preceding the DIR core. The bypass multiplexer allows for one of the four line receiver outputs to be

routed to the line driver or buffer output, thereby providing a bypass mode of operation. Both the line driver and

CMOS output buffer include output disables, set by the TXOFF and AESOFF bits in control register 0x08. When

the outputs are disabled, they are forced to a low logic state.

The AES3 encoder includes an output mute function that sets all bits for both the Channel 1 and 2 audio and

auxiliary data to zero. The preamble, V, U, and C bits are unaffected, while the P bit is recalculated. The mute

function is controlled using the TXMUTE bit in control register 0x08.

Figure 11. Digital Interface Transmitter (DIT) Functional Block Diagram

The AES3 encoder includes a block start input/output pin, BLS (pin 35). The BLS pin may be programmed as an

input or output. The input/output state of the BLS pin is programmed using the BLSM bit in control register 0x07.

By default, the BLS pin is configured as an input.

As an input, the BLS pin may be used to force a block start condition, whereby the start of a new block of

channel status and user data is initiated by generating a Z preamble for the next frame of data. The BLS input

must be synchronized with the DIT internal SYNC clock. This clock is output on SYNC (pin 36). The SYNC clock

rising edge is aligned with the start of each frame for the AES3-encoded data output by the DIT. Figure 12 shows

the format required for an external block start signal, as well as indicating the format when the BLS pin is

configured as an output. When the BLS pin is an output, the DIT generates the block start signal based upon the

internal SYNC clock.

For details regarding DIT control and status registers, as well as channel status and user data buffers, refer to

Control Registers and Channel Status and User Data Buffer Maps.

DIX4192 Datasheet(PDF) 18 Page - Texas Instruments

DIX4192 Datasheet(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

Datasheet Download

Link URL