8

ISO5451-Q1

SLLSEQ3A – SEPTEMBER 2016 – REVISED DECEMBER 2016

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Copyright © 2016, Texas Instruments Incorporated

(1)

IIH for IN–, RST pin is zero as they are pulled high internally.

(2)

IIL for IN+ is zero, as it is pulled low internally.

7.9 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 –

GND2 = 15 V, GND2 – VEE2 = 8 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOLTAGE SUPPLY

VIT+(UVLO1)

Positive-going UVLO1 threshold voltage

input side (VCC1 – GND1)

2.25

V

VIT-(UVLO1)

Negative-going UVLO1 threshold voltage

input side (VCC1 – GND1)

1.7

V

VHYS(UVLO1)

UVLO1 Hysteresis voltage (VIT+ – VIT–)

input side

0.24

V

VIT+(UVLO2)

Positive-going UVLO2 threshold voltage

output side (VCC2 – GND2)

12

13

V

VIT-(UVLO2)

Negative-going UVLO2 threshold voltage

output side (VCC2 – GND2)

9.5

11

V

VHYS(UVLO2)

UVLO2 Hysteresis voltage (VIT+ – VIT–)

output side

1

V

IQ1

Input supply quiescent current

2.8

4.5

mA

IQ2

Output supply quiescent current

3.6

6

mA

LOGIC I/O

VIT+(IN,RST)

Positive-going input threshold voltage (IN+,

IN–, RST)

0.7 × VCC1

V

VIT-(IN,RST)

Negative-going input threshold voltage

(IN+, IN–, RST)

0.3 × VCC1

V

VHYS(IN,RST)

Input hysteresis voltage (IN+, IN–, RST)

0.15 × VCC1

V

IIH

High-level input leakage at (IN+) (1)

IN+ = VCC1

100

µA

IIL

Low-level input leakage at (IN–, RST) (2)

IN– = GND1, RST = GND1

–100

µA

IPU

Pull-up current of FLT, RDY

V(RDY) = GND1, V(FLT) = GND1

100

µA

VOL

Low-level output voltage at FLT, RDY

I(FLT) = 5 mA

0.2

V

GATE DRIVER STAGE

V(OUTPD)

Active output pulldown voltage

IOUT = 200 mA, VCC2 = open

2

V

V(OUTH)

High-level output voltage

IOUT = –20 mA

VCC2 – 0.5

VCC2 – 0.24

V

V(OUTL)

Low-level output voltage

IOUT = 20 mA

VEE2 + 13

VEE2 + 50

mV

I(OUTH)

High-level output peak current

IN+ = high, IN– = low,

VOUT = VCC2 - 15 V

1.5

2.5

A

I(OUTL)

Low-level output peak current

IN+ = low, IN– = high,

VOUT = VEE2 + 15 V

3.4

5

A

ACTIVE MILLER CLAMP

V(CLP)

Low-level clamp voltage

I(CLP) = 20 mA

VEE2 + 0.015

VEE2 + 0.08

V

I(CLP)

Low-level clamp current

V(CLAMP) = VEE2 + 2.5 V

1.6

2.5

A

V(CLTH)

Clamp threshold voltage

1.6

2.1

2.5

V

SHORT CIRCUIT CLAMPING

V(CLP_OUT)

Clamping voltage

(VOUT - VCC2)

IN+ = high, IN– = low, tCLP=10 µs,

I(OUTH) = 500 mA

0.8

1.3

V

V(CLP_CLAMP)

Clamping voltage

(VCLP - VCC2)

IN+ = high, IN– = low, tCLP=10 µs,

I(CLP) = 500 mA

1.3

V

V(CLP_CLAMP)

Clamping voltage at CLAMP

IN+ = High, IN– = Low, I(CLP) = 20

mA

0.7

1.1

V

DESAT PROTECTION

I(CHG)

Blanking capacitor charge current

V(DESAT) - GND2 = 2 V

0.42

0.5

0.58

mA

I(DCHG)

Blanking capacitor discharge current

V(DESAT) - GND2 = 6 V

9

14

mA

V(DSTH)

DESAT threshold voltage with respect to

GND2

8.3

9

9.5

V

V(DSL)

DESAT voltage with respect to GND2,

when OUT is driven low

0.4

1

V