P

L

OUT

1

F

2

R

C



K 5 K

K

LP38500-ADJ, LP38502-ADJ

www.ti.com

SNVS539H – NOVEMBER 2007 – REVISED SEPTEMBER 2015

Feature Description (continued)

Figure 15. Gain-Bandwidth Plot for No Load

The reduction in unity-gain bandwidth as load current is reduced is normal for any LDO regulator using a P-FET

or PNP pass transistor, because they have a pole in the loop gain function given by:

(1)

This illustrates how the pole goes to the highest frequency when RL is minimum value (maximum load current).

In general, LDOs have maximum bandwidth (and lowest phase margin) at full load current. In the case of the

LP38500-ADJ or LP38502-ADJ, it can be seen that it has good phase margin even when using ceramic

capacitors with ESR values of only a few m

Ω.

7.3.2 Load Transient Response

Load transient response is defined as the change in regulated output voltage which occurs as a result of a

change in load current. Many applications have loads which vary, and the control loop of the voltage regulator

must adjust the current in the pass FET transistor in response to load current changes. For this reason,

regulators with wider bandwidths often have better transient response.

The LP38500-ADJ and LP38502-ADJ employs an internal feed-forward design which makes the load transient

response much faster than would be predicted simply by loop speed: this feedforward means any voltage

changes appearing on the output are coupled through to the high-speed driver used to control the gate of the

pass FET along a signal path using very fast FET devices. Because of this, the pass transistor’s current can

change very quickly.

Figure 15 shows the output voltage load transient which occurs on a 1.8-V output when the load changes from

0.1 A to 1.5 A at an average slew rate of 0.5 A/µs. As shown, the peak output voltage change from nominal is

about 40 mV, which is about 2.2%.

Figure 16. Load Transient Response

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