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DLPR410 Datasheet(PDF) 16 Page - Texas Instruments |
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DLPR410 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 53 page  tc DCLK_N DCLK_P D_N(0:?) D_P(0:?) tw tw th tsu th tsu 50% 50% SCTRL_N SCTRL_P th tsu th tsu 50% Not to Scale tc DCLK_N DCLK_P D_N(0:?) D_P(0:?) tw tw th tsu th tsu 50% SCTRL_N SCTRL_P th tsu th tsu t skew 50% 50% 16 DLP650LNIR DLPS136 – NOVEMBER 2018 www.ti.com Product Folder Links: DLP650LNIR Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Uniformly distributed within area shown in Figure 8. Figure 7. Timing Requirements See Timing Requirements for timing requirements and LVDS pairs per channel (bus) defining D_P(0:x) and D_N(0:x). 6.8 System Mounting Interface Loads Table 1. System Mounting Interface Loads PARAMETER MIN NOM MAX UNIT Condition 1: • Thermal Interface area(1) 11.3 kg • Electrical Interface area(1) 11.3 kg Condition 2: • Thermal Interface area(1) 0 kg • Electrical Interface area(1) 22.6 kg |
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