DLPR410 datasheet(24/53 Pages) TI2

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DLP650LNIR

DLPS136 – NOVEMBER 2018

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Table 4. Input/Output Description

PIN NAME

DESCRIPTION

I/O

ARST

Asynchronous active low reset

CLKIN_R

Reference clock, 50 MHz

DIN_[A,B,C,D](15:0)

LVDS DDR input for data bus A,B,C,D (15:0)

DCLKIN[A,B,C,D]

LVDS inputs for data clock (400 MHz) on bus A, B, C, and D

DVALID[A,B,C,D]

LVDS input signals used to start write sequence for bus A, B, C, and D

ROWMD(1:0)

DMD row address and row counter control

ROWAD(10:0)

DMD row address pointer

BLK_AD(3:0)

DMD mirror block address pointer

BLK_MD(1:0)

DMD mirror block reset and clear command modes

PWR_FLOAT

Used to float DMD mirrors before complete loss of power

LOAD4

Load4 mode enable [uses DLPC410 SPARE_0 input pin (AB21)]

DMD_TYPE(3:0)

DMD type in use

RST_ACTIVE

Indicates DMD mirror reset in progress

INIT_ACTIVE

Initialization in progress.

VLED0

System “heartbeat” signal

VLED1

Denotes initialization complete

7.3.4.1.1.2

Initialization

The INIT_ACTIVE (Table 4) signal indicates that the DLP650LNIR, DLPA200, and DLPC410 are in an

initialization state after power is applied. During this initialization period, the DLPC410 is initializing the

DLP650LNIR and DLPA200 by setting all internal registers to their correct states. When this signal goes low, the

system has completed initialization. System initialization takes approximately 220 ms to complete. Data and

command write cycles should not be asserted during the initialization.

During initialization the user must send a training pattern to the DLPC410 on all data and DVALID lines to

correctly align the data inputs to the data clock. For more information, see the interface training pattern

information in the DLPC410 data sheet.

7.3.4.1.1.3

DMD Device Detection

The DLPC410 automatically detects the DMD type and device ID. DMD_TYPE (Table 4) is an output from the

DLPC410 that contains the DMD information.

7.3.4.1.1.4

Power Down

To ensure long term reliability of the DLP650LNIR DMD, a shutdown procedure must be executed. Prior to power

removal, assert the PWR_FLOAT (Table 4) signal and allow approximately 300 µs to assure the mirrors are in a

flat state prior to power removal.

NOTE

Use PWR_FLOAT only when DC power is going to be removed from the DMD. When not

powering down but it is desired to place the system in an idle (non-functioning) state, all

applications benefit from operating the DMD near 50% landed on/off duty cycle. See

section 3 (Duty Cycle Considerations) in application note DLPA052 - System Design

Considerations Using TI DLP® Technology down to 400 nm.

7.3.4.1.2

DLPC410 to DMD Interface

7.3.4.1.2.1

DLPC410 to DMD IO Description

Table 5 lists the available controls and status pin names and their corresponding signal type, along with a brief

functional description.

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