DLPR410 datasheet(42/53 Pages) TI2

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DLP650LNIR

DLPS136 – NOVEMBER 2018

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10.1.4.1 Trace Length Matching

The DLPC410 DMD data signals require precise length matching. Make sure differential signals have impedance

of 100

Ω (with 5% tolerance). It is important that the propagation delays are matched. The maximum differential

pair uncoupled length is 100 mils with a relative propagation delay of ±25 mil between the p and n. Matching all

signals exactly maximizes the channel margin. The signal path through all boards, flexible cables and internal

DMD routing must be considered in this calculation.

10.1.5 DLP650LNIR Decoupling

Make sure to distribute general decoupling capacitors for the DLP650LNIR around the PCB and place them to

minimize the distance from device voltage and ground pads. Each decoupling capacitor (0.1 µF recommended)

needs vias directly to the ground and power planes. Via sharing between components (discreet or integrated) is

discouraged. Tie the power and ground pads of the DLP650LNIR to the voltage and ground planes with their

own vias.

10.1.5.1 Decoupling Capacitors

Place decoupling capacitors so that they minimize the distance from the decoupling capacitor to the supply and

ground pin of the component. Follow these specific guidelines:

•

Locate the supply voltage pin of the capacitor close to the DMD supply voltage pin(s). The decoupling

capacitor needs vias to ground and voltage planes. The DMD can be connected directly to the decoupling

capacitor (no via) if the trace length is less than 0.1 inch. Otherwise, tie the component to the voltage or

ground plane through separate vias.

•

Make sure that the trace lengths of the voltage and ground connections for decoupling capacitors and

components is less than 0.1 inch to minimize inductance.

•

Make the trace width of the power and ground connection to decoupling capacitors and components as wide

as possible to minimize inductance.

•

Connecting decoupling capacitors to ground and power planes through multiple vias can reduce inductance

and improve noise performance.

•

Decoupling performance can be improved by utilizing low ESR and low ESL capacitors.

10.1.6 VCC and VCC2

Connect the VCC pins of the DMD directly to the DMD VCC plane. Distribut the decoupling for the VCC around

the DMD and placed to minimize the distance from the voltage and ground pads. Each decoupling capacitor

needs vias directly connected to the ground and power planes. Tie the VCC and GND pads of the DMD to the

VCC and ground planes with their own vias.

The VCC2 voltage can be routed to the DMD as a wide trace. Place decoupling capacitors to minimize the

distance from the VCC2 and ground pads of the DMD. Use wide etch from the decoupling capacitors to the DMD

connection to reduce inductance and improves decoupling performance.

10.1.7 DMD Layout

See the respective sections in this data sheet for package dimensions, timing and pin out information.

10.1.8 DLPA200

The DLPA200 driver generates the micromirror clocking pulses for the DMD. Route the DMD-drive outputs from

the DLPA200 (MBRST[15:0] with a minimum trace width of 11 mil and a minimum spacing of 15 mil. Route the

VCC and VCC2 traces from the output capacitors to the DLPA200 with a minimum trace width and spacing of 11

mil and 15 mil, respectively. See the DLPA200 customer data sheet for mechanical package and layout

information.

10.2 Layout Example

For LVDS (and other differential signal) pairs and groups, it is important to match trace lengths. In the area of the

dashed lines, Figure 22 shows correct matching of signal pair lengths with serpentine sections to maintain the

correct impedance.

DLPR410 Datasheet(PDF) 42 Page - Texas Instruments

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