DLPR410 datasheet(9/53 Pages) TI2

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DLP650LNIR

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DLPS136 – NOVEMBER 2018

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(1)

The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(2)

Limit exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of

CTELR.

6.2 Storage Conditions

Applicable for the DMD as a component or non-operating in a system.

MIN

MAX

UNIT

TDMD

DMD storage temperature

–40

°C

TDP-AVG

Average dew point temperature (non-condensing) (1)

°C

TDP-ELR

Elevated dew point temperature range (non-condensing) (2)

°C

CTELR

Cumulative time in elevated dew point temperature range

Months

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic

discharge

Human-body model (HBM), per

ANSI/ESDA/JEDEC JS-001(1)

All pins except MBRST(15:0)

±2000

Pins MBRST(15:0)

< 250

(1)

All voltages are referenced to VSS (common ground). VCC, VCCI, VCC2, and VMBRST power supplies are all required for proper DMD

operation. VSS must also be connected to common ground.

(2)

VCC2 supply transients must fall within specified max voltages.

(3)

To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than the specified limit.

(4)

PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the

SCPDO output pin.

(5)

The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(6)

See Figure 3.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this

data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied

when operating the device above or below these limits.

MIN NOM

MAX

UNIT

VOLTAGE SUPPLY

VCC

Supply voltage for LVCMOS core logic(1)

3.0

3.3

3.6

VCCI

Supply voltage for LVDS Interface (1)

3.0

3.3

3.6

VCC2

Micromirror Electrode and HVCMOS voltage(1)(2)

8.25

8.5

8.75

VMBRST

Micromirror Bias / Reset Voltage(1)

–27

26.5

|VCC – VCCI|

Supply voltage delta (absolute value)(3)

0.3

LVCMOS INTERFACE

VIH

Input High Voltage

1.7

2.5

VCC + 0.3

VIL

Input Low Voltage

–0.3

0.7

IOH

High Level Output Current

–20

IOL

Low Level Output Current

tPWRDNZ

PWRDNZ pulse width(4)

SCP INTERFACE

ƒSCPCLK

SCP clock frequency(5)

500

kHz

tSCP_PD

Propagation delay, clock to Q, from rising-edge of SCPCLK to

valid SCPDO.(6)

900

tSCP_DS

SCPDI clock setup time (before SCPCLK falling-edge) (6)

800

tSCP_DH

SCPDI hold time (after SCPCLK falling-edge)(6)

900

tSCP_NEG_ENZ

Time between falling–edge of SCPENZ and the rising–edge of

SCPCLK.(5)

SCP_POS_ENZ

Time between falling-edge of SCPCLK and the rising–edge of

SCPENZ

tSCP_OUT_EN

Time required for SCP output buffer to recover after SCPENZ

(from tri-state).

192/ƒDCLK

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