DLPR410 datasheet(41/53 Pages) TI2

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DLP650LNIR

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DLPS136 – NOVEMBER 2018

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10 Layout

10.1 Layout Guidelines

The DLP650LNIR is a component of a chipset that is controlled by the DLPC410 in conjunction with the

DLPA200. These guidelines refer to a PCB board with these components.

A target impedance of 50

Ω for single-ended signals and 100 Ω between LVDS signals is specified for all signal

layers.

10.1.1 Impedance Requirements

Make sure to route signals to have a matched impedance of 50 Ω ±10% except for LVDS differential pairs

(D_Xnn, DCLK_Xn, and SCTRL_Xn). Match the differential pairs to 100 Ω ±10% across each pair.

10.1.2 PCB Signal Routing

When designing a PCB for the DLP650LNIR controlled by the DLPC410 in conjunction with the DLPA200, the

following are recommended:

Make sure that signal trace corners are no sharper than 45°. Make sure that adjacent signal layers have the

predominate traces routed orthogonal to each other. TI recommends that critical signals be hand routed in the

following order: DMD (LVDS signals), then DLPA200 signals.

TI does not recommend signal routing on power or ground planes.

TI does not recommend ground plane slots.

Make sure that high-speed signal traces do not cross over slots in adjacent power and/or ground planes.

Table 9. Important Signal Trace Constraints

SIGNAL

CONSTRAINTS

LVDS (D_Xnn,

DCLK_xn, and SCTRL_xn)

P-to-N data, clock, and SCTRL: <10 mils (0.25 mm); Pair-to-pair <10 mils (0.25 mm); Bundle-to-bundle

<2000 mils (50 mm, for example D_Ann to D_Bnn)

Trace width: 4 mil (0.1 mm)

Trace spacing: In ball field – 4 mil (0.11 mm); PCB etch – 14 mil (0.36 mm)

Maximum recommended trace length <6 inches (150 mm)

Table 10. Power Trace Widths and Spacing

SIGNAL NAME

MINIMUM TRACE

WIDTH

MINIMUM TRACE

SPACING

LAYOUT REQUIREMENTS

GND

Maximize

5 mil (0.13 mm)

Maximize trace width to connecting pin as a minimum

VCC, VCC2

20 mil (0.51 mm)

10 mil (0.25 mm)

MBRST[15:0]

11 mil (0.23 mm)

15 mil (0.38 mm)

10.1.3 Fiducials

Make sure that the fiducials for automatic component insertion are 0.05-inch copper with a 0.1-inch cutout

(antipad). Fiducials for optical auto insertion are placed on three corners of both sides of the PCB.

10.1.4 DMD Interface

The digital interface from the DLPC410 to the DMD are LVDS signals that run at clock rates up to 400 MHz. Data

is clocked into the DMD on both the rising and falling edge of the clock, so the data rate is 800 MHz. Make sure

the LVDS signals have 100

Ω differential impedance. Make sure the differential signals are length-matched and

are as short as possible. Parallel termination at the LVDS receiver is in the DMD; therefore, on board termination

is not necessary.

DLPR410 Datasheet(PDF) 41 Page - Texas Instruments

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