LP8754 datasheet(19/52 Pages) TI2

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LDO

(internal)

NRST

tI2CT

LP8754 receiving/sending data across the system I

2C bus.

VVDDA5V

VVIOSYS

FREQUENCY

LP8754

www.ti.com

SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014

Features Descriptions (continued)

Where a fixed-frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread

spectrum architecture of the LP8754 spreads that energy over a large bandwidth.

Figure 10. Spread Spectrum Modulation

7.3.2 Power-Up and Output Voltage Sequencing

The power-up sequence for the LP8754 is as follows:

•

VVINBXX and VVDDA5V reach min recommended levels.

•

VVIOSYS set high. Enables the system I/O interface. For power-on-reset (POR), the I

2C host should allow at

least 500 µs before sending data to the LP8754 after the rising edge of the VIOSYS line.

•

VLDO voltage is raising. The LDO voltage is generated internally. The internal POR signal is activated.

•

Internal POR deasserted, OTP read.

•

Device enters standby mode.

•

DC/DC enable, output voltage, voltage slew rate programmed over I2C as needed by the application.

•

NRST set high. The DC/DC converter can be enabled and disabled by VSET_B0.EN_DIS_B0 bit or using the

NRST signal.

Figure 11. Timing Diagram for the Power-Up Sequence

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LP8754 Datasheet(PDF) 19 Page - Texas Instruments