1

NRST

VVIOSYS

VVDDA5V

NRST

2

VVIOSYS

VVDDA5V

LP8754

SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014

www.ti.com

Features Descriptions (continued)

Table 1. Power-Up Sequence

SYMBOL

PARAMETER

CONDITION(1)

MIN

TYP

MAX

UNIT

t0

VVDDA5V to VVIOSYS assertion

0

µs

t1

LDOON Delay Time

CLDO = 1 µF

<100

150

µs

t2

LDOON to NRST HIGH

0

µs

tI2CT

Device ready for I2C data transfer

500

µs

(1)

These specification table entries are specified by design. The power input lines VVINBXX, VVDDA5V and VVIOSYS must be stable before the

NRST line goes High. Also, the VLDO line must be stable 1.8 V before the NRST line goes High.

7.3.3 Device Reset Scenarios

There are three reset methods implemented on the LP8754:

•

Software reset

•

Hardware reset

•

Power-on reset (POR)

An SW-reset occurs when the RESET.SW_RESET bit is written first with 1, followed by 0 right after that. This

event resets the control registers shown in Table 2 to the default values. The temperature, power good, and

other faults are persistent over the SW reset to allow for the system to identify to cause of the failure.

An internal power-on reset (POR) occurs when the supply voltage (VVDDA5V) transitions above the POR threshold

or VVIOSYS is toggled low/high. Each of the registers contain a factory-defined value upon POR, and this data

remains there until any of the following occurs:

•

Device sets a Flag bit, causing the Status register to be updated. The other registers remain untouched.

•

A different data word is written to a writable register.

The internal registers will lose their contents if the supply voltage (VVDDA5V) goes below 1 V (typ.).

A hardware reset is accomplished by NRST low. This event resets the control registers shown in Table 2 to the

default values.

Under OVP, UVLO, TSD, or VVIOSYS low (while NRST still high) conditions, a Fast Power-Down is launched.

Normal Power-Down Sequence Follows This Event

(Marked as '1')

Fast Power-Down Follows This Event

Figure 12. The External Power Control System De-

Figure 13. NRST Stays HIGH While VVIOSYS

asserts NRST

Transition from HIGH to LOW Happens (Marked as

'2')

20

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